A new ATPG technique (ExpoTan) for testing analog circuits

被引:16
|
作者
Varaprasad, B. K. S. V. L. [1 ]
Patnaik, L. M.
Jamadagni, H. S.
Agrawal, V. K.
机构
[1] ISRO, Micro Elect Design Facil, Satellite Ctr, Bangalore 560017, Karnataka, India
[2] Indian Inst Sci, Dept Comp Sci & Automat, Microproc Applicat Lab, Bangalore 560012, Karnataka, India
[3] Indian Inst Sci, Ctr Elect Design & Technol, Bangalore 560012, Karnataka, India
关键词
analog built-in self-test (BIST); automatic test-pattern; generation (ATPG); sinusoidal steady-state testing; test-set compaction;
D O I
10.1109/TCAD.2006.882596
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In analog testing, usage of a single sinusoid as a test signal when compared to multitone signal, and fault detection with digital counting technique, facilitate the test implementation with simple built-in self-test hardware and make testing more cost effective. In this paper, a novel test-set-selection technique known as ExpoTan for testing linear-time-invariant (LTI) circuits is presented. The authors formulate the test generation problem with tan(-1) () and exponential functions for identification of a test signal with maximum fault coverage. For identification of a test signal the ExpoTan technique combines test generation and test-set-compaction tasks in a single phase and generates an efficient compacted test set. The experimental results show that the testing of LTI circuits using ExpoTan technique for the benchmark circuits achieves the required fault coverage with shorter testing time and test generation time.
引用
收藏
页码:189 / 196
页数:8
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