Optimization of phase-locked loop circuits via geometric programming

被引：37

作者：

Colleran, DM ^{[1
]}

Portmann, C ^{[1
]}

Hassibi, A ^{[1
]}

Crusius, C ^{[1
]}

Mohan, SS ^{[1
]}

Boyd, S ^{[1
]}

Lee, TH ^{[1
]}

Hershenson, MD ^{[1
]}

机构：

[1] Barcelona Design Inc, Newark, CA 94560 USA

来源：

PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/CICC.2003.1249422

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We describe the global optimization of phase-locked loop (PLL) circuits using geometric programming (GP). Equations for the jitter, frequency range, and power of the PLL are presented in GP form. An array of PLL circuits was automatically generated using this technique in a 0.18 mum, 1.8V CMOS process. Silicon measurements show good agreement with the model. The results include a 1.9GHz PLL with a period jitter of 2.2ps RMS and an accumulated jitter of 6.2ps RMS, consuming 10.8mW.

引用

页码：377 / 380

页数：4

共 50 条

[1] Optimization of bandwidth for phase-locked loop in OTU
Yuan, Jian-Guo
Li, Hao
He, Qing-Ping
[J]. Guangxue Jingmi Gongcheng/Optics and Precision Engineering, 2011, 19 (08): : 1937 - 1943
[2] PHASE-LOCKED LOOP
MCLEAN, D
[J]. CONTROL, 1967, 11 (109): : 339 - &
[3] A phase-locked loop
Shahruz, SM
[J]. REVIEW OF SCIENTIFIC INSTRUMENTS, 2001, 72 (03): : 1888 - 1892
[4] Simulation of the classical analog phase-locked loop based circuits
Kuznetsov, N. V.
Leonov, G. A.
Yuldashev, M. V.
Yuldashev, R. V.
[J]. IFAC PAPERSONLINE, 2015, 48 (01): : 568 - 573
[5] CMOS Phase-Locked Loop Circuits and Hot Carrier Effects
Liu, Yang
Srivastava, Ashok
[J]. JOURNAL OF LOW POWER ELECTRONICS, 2012, 8 (03) : 304 - 316
[6] BIFURCATION AND FRACTAL BASIN BOUNDARIES OF PHASE-LOCKED LOOP CIRCUITS
ENDO, T
CHUA, LO
[J]. 1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 1989, : 820 - 825
[7] Phase-locked loop architecture for adaptive jitter optimization
Vamvakos, SD
Werner, C
Nikolic, B
[J]. 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, PROCEEDINGS, 2004, : 161 - 164
[8] Nonlinear Phase-Locked Loop Design using Semidefinite Programming
Wang, Ta-Chung
Chiou, Tsung-Yu
Lall, Sanjay
[J]. 2008 MEDITERRANEAN CONFERENCE ON CONTROL AUTOMATION, VOLS 1-4, 2008, : 1047 - +
[9] BIFURCATION DIAGRAMS AND FRACTAL BASIN BOUNDARIES OF PHASE-LOCKED LOOP CIRCUITS
ENDO, T
CHUA, LO
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1990, 37 (04): : 534 - 540
[10] Linear Phase-Locked Loop
Miskovic, Vlatko
Blasko, Vladimir
Jahns, Thomas M.
Lorenz, Robert D.
Jorgensen, Per M.
[J]. 2018 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE), 2018, : 5677 - 5683

← 1 2 3 4 5 →