Optimization of phase-locked loop circuits via geometric programming

被引：37

作者：

Colleran, DM ^{[1
]}

Portmann, C ^{[1
]}

Hassibi, A ^{[1
]}

Crusius, C ^{[1
]}

Mohan, SS ^{[1
]}

Boyd, S ^{[1
]}

Lee, TH ^{[1
]}

Hershenson, MD ^{[1
]}

机构：

[1] Barcelona Design Inc, Newark, CA 94560 USA

来源：

PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/CICC.2003.1249422

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We describe the global optimization of phase-locked loop (PLL) circuits using geometric programming (GP). Equations for the jitter, frequency range, and power of the PLL are presented in GP form. An array of PLL circuits was automatically generated using this technique in a 0.18 mum, 1.8V CMOS process. Silicon measurements show good agreement with the model. The results include a 1.9GHz PLL with a period jitter of 2.2ps RMS and an accumulated jitter of 6.2ps RMS, consuming 10.8mW.

引用

页码：377 / 380

页数：4

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