A Novel Phase-locked Loop for HVDC

Phase locked loop (PLL) is the basis of HVDC control system. PLL ability to track commutating voltage phase directly affects the regulation of HVDC control system, then producing an effect on performance of HVDC transmission. A novel PLL is proposed to solve the problems of slow dynamic performance and large frequency fluctuation during the faults in existing HVDC project's PLLs. This PLL uses multiple delay signal cancellation algorithm as pre-filter to extract fundamental positive sequence voltage component. In order to reduce the fluctuation of PLL frequency during faults, the PLL output frequency is fixed when the fault is detected by the fault detector. As a consequence, the PLL tracking speed to the phase is accelerated. Simulation results indicate that the proposed PLL shows excellent performance under the conditions of phase jump, voltage distortion and frequency offset. Finally, the proposed PLL is applied to CIGRE HVDC Benchmark system, effectively reducing the probability of subsequent commutation failure in HVDC. © 2019, Power System Technology Press. All right reserved.