Can SAT be used to improve sequential ATPG methods?

被引：2

作者：

Prasad, MR ^{[1
]}

Hsiao, MS ^{[1
]}

Jain, J ^{[1
]}

机构：

[1] Fujitsu Labs Amer, Sunnyvale, CA USA

来源：

17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA | 2004年

关键词：

D O I：

10.1109/ICVD.2004.1260982

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this work we investigate the integration of SAT methods into a simulation-based sequential ATPG tool, STRATEGATE [11], with the aim of improving the state-of-the-art in sequential ATPG. We offer a detailed analysis of possible scenarios and algorithms for performing such an integration. Our preliminary investigations show that such hybrid approaches can be very promising.

引用

页码：585 / 590

页数：6

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