Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control

被引:3
|
作者
Chowdhury, Prattay [1 ]
Schafer, Benjamin Carrion [1 ]
机构
[1] Univ Texas Dallas, 800 W Campbell Rd, Richardson, TX 75080 USA
关键词
Approximate computing; dynamic error control; voltage overscaling; low-power; high-level synthesis; resource sharing; SKEWNESS; KURTOSIS;
D O I
10.1145/3473909
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Approximate Computing has emerged as an alternative way to further reduce the power consumption of integrated circuits (ICs) by trading off errors at the output with simpler, more efficient logic. So far the main approaches in approximate computing have been to simplify the hardware circuit by pruning the circuit until the maximum error threshold is met. One of the critical issues, though, is the training data used to prune the circuit. The output error can significantly exceed the maximum error if the final workload does not match the training data. Thus, most previous work typically assumes that training data matches with the workload data distribution. In this work, we present a method that dynamically overscales the supply voltage based on different workload distribution at runtime. This allows to adaptively select the supply voltage that leads to the largest power savings while ensuring that the error will never exceed the maximum error threshold. This approach also allows restoring of the original error-free circuit if no matching workload distribution is found. The proposed method also leverages the ability of High-Level Synthesis (HIS) to automatically generate circuits with different properties by setting different synthesis constraints to maximize the available timing slack and, hence, maximize the power savings. Experimental results show that our proposed method works very well, saving on average 47.08% of power as compared to the exact output circuit and 20.25% more than a traditional approximation method.
引用
收藏
页数:18
相关论文
共 50 条
  • [41] Multi-Pumping for Resource Reduction in FPGA High-Level Synthesis
    Canis, Andrew
    Anderson, Jason H.
    Brown, Stephen D.
    DESIGN, AUTOMATION & TEST IN EUROPE, 2013, : 194 - 197
  • [42] Temperature-aware resource allocation and binding in high-level synthesis
    Mukherjee, R
    Memik, SO
    Memik, G
    42nd Design Automation Conference, Proceedings 2005, 2005, : 196 - 201
  • [43] High-Level Synthesis of Resource-oriented Approximate Designs for FPGAs
    Leipnitz, Marcos T.
    Nazar, Gabriel L.
    PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2019,
  • [44] Automatic Control Synthesis for Swarm Robots from Formation and Location-based High-level Specifications
    Chen, Ji
    Wang, Hanlin
    Rubenstein, Michael
    Kress-Gazit, Hadas
    2020 IEEE/RSJ INTERNATIONAL CONFERENCE ON INTELLIGENT ROBOTS AND SYSTEMS (IROS), 2020, : 8027 - 8034
  • [45] Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis
    Perina, Andre B.
    Silitonga, Arthur
    Becker, Jurgen
    Bonato, Vanderlei
    IEEE TRANSACTIONS ON COMPUTERS, 2021, 70 (12) : 2070 - 2082
  • [46] Thread Weaving: Static Resource Scheduling for Multithreaded High-Level Synthesis
    Hsiao, Hsuan
    Anderson, Jason
    PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2019,
  • [47] Performance and Resource Modeling for FPGAs using High-Level Synthesis tools
    Da Silva, Bruno
    Braeken, An
    D'Hollander, Erik H.
    Touhafi, Abdellah
    PARALLEL COMPUTING: ACCELERATING COMPUTATIONAL SCIENCE AND ENGINEERING (CSE), 2014, 25 : 523 - 531
  • [48] On multiple-voltage high-level synthesis using algorithmic transformations
    Dung, LR
    Yang, HC
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2004, E87A (12) : 3100 - 3108
  • [49] On multiple-voltage high-level synthesis using algorithmic transformations
    Yang, Hsueh-Chih
    Dung, Lan-Rong
    ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 872 - 876
  • [50] Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis
    Ferretti, Lorenzo
    Kwon, Jihye
    Ansaloni, Giovanni
    Di Guglielmo, Giuseppe
    Carloni, Luca P.
    Pozzi, Laura
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (11) : 3736 - 3747