A Fast and Accurate Geometric Programming Technique for Analog Circuits Sizing

In this paper, a fast optimization technique for CMOS analog circuits sizing is presented. The technique is based on geometric programming (GP) optimization. Although GP sizing is a very fast method, it produces inaccurate optimal solution due to the lack of accurate MOSFET equations. The proposed technique generates accurate geometric programming (GP) compatible MOSFET equations. Generation of device equations has two phases; look-up table (LUT) generation phase and monomial data fitting phase. The first phase is completed once per technology model. The second phase is performed during the circuit optimization process. A two-stage op-amp is optimized to test the performance of the proposed technique. The simulation results show that the circuit performance achieved using the proposed technique is better than the circuit performance reported in literature, and that the optimal solution is found in less computation time.