Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

被引：0

作者：

Barraud, S. ^{[1
,2
]}

Previtali, B. ^{[1
,2
]}

Lapras, V. ^{[1
,2
]}

Vizioz, C. ^{[1
,2
]}

Hartmann, J. -M. ^{[1
,2
]}

Martinie, S. ^{[1
,2
]}

Lacord, J. ^{[1
,2
]}

Casse, M. ^{[1
,2
]}

Dourthe, L. ^{[1
,2
]}

Loup, V. ^{[1
,2
]}

Romano, G. ^{[3
]}

Rambal, N. ^{[1
,2
]}

Chalupa, Z. ^{[1
,2
]}

Bernier, N. ^{[1
,2
]}

Audoit, G. ^{[1
,2
]}

Jannaud, A. ^{[4
]}

Delaye, V. ^{[1
,2
]}

Balan, V. ^{[1
,2
]}

Rozeau, O. ^{[1
,2
]}

Ernst, T. ^{[1
,2
]}

Vinet, M. ^{[1
,2
]}

机构：

[1] CEA, LETI, Minatec Campus, F-38054 Grenoble, France

[2] Univ Grenoble Alpes, Minatec Campus, F-38054 Grenoble, France

[3] STMicroelectronics, F-38926 Crolles, France

[4] SERMA Technol, Minatec Campus, F-38054 Grenoble, France

来源：

2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, a comprehensive study going from the integration of 3D stacked nanosheets Gate-All-Around (GAA) MOSFET devices to SPICE modeling is proposed. Devices have been successfully fabricated on SOI substrates using a replacement high-kappa metal gate process and self-aligned-contacts. Back biasing is herein efficiently used to highlight a drastic improvement of electrostatics in the upper GAA Si channels. Advanced electrical characterization of these devices enabled us to calibrate a new version of physical compact model (LETI-NSP) in order to assess the performance of ring oscillators for different configurations of GAA FETs integrating up to 8 vertically stacked Si channels.

引用

页数：4

共 50 条

[41] Comparative analysis of capacitorless DRAM performance according to stacked junctionless gate-all-around structures
Hwang, Jihye
Yun, Ilgu
[J]. Solid-State Electronics, 2025, 223
[42] Three dimensionally stacked SiGe nanowire array and Gate-All-Around p-MOSFETs
Bera, L. K.
Nguyen, H. S.
Singh, N.
Liow, T. Y.
Huang, D. X.
Hoe, K. M.
Tung, C. H.
Fang, W. W.
Rustagi, S. C.
Jiang, Y.
Lo, G. Q.
Balasubramanian, N.
Kwong, D. L.
[J]. 2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2006, : 298 - 301
[43] Performance Evaluation of Stacked Gate-All-Around MOSFETs at 7 and 10 nm Technology Nodes
Wu, Meng-Yen
Chiang, Meng-Hsueh
[J]. PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016, 2016, : 169 - 172
[44] First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs
Capogreco, E.
Witters, L.
Arimura, H.
Sebaai, F.
Porret, C.
Hikavyy, A.
Loo, R.
Milenin, A. P.
Eneman, G.
Favia, P.
Bender, H.
Wostyn, K.
Litta, E. Dentoni
Schulze, A.
Vrancken, C.
Opdebeeck, A.
Mitard, J.
Langer, R.
Holsteyns, F.
Waldron, N.
Barla, K.
De Heyn, V.
Mocuta, D.
Collaert, N.
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (11) : 5145 - 5150
[45] Vertically Stacked Gate-All-Around Structured Tunneling-Based Ternary-CMOS
Kim, Sihyun
Lee, Kitae
Lee, Jong-Ho
Kwon, Daewoong
Park, Byung-Gook
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (09) : 3889 - 3893
[46] Performance Analysis of Sub-10nm Vertically Stacked Gate-All-Around FETs
Mohapatra, E.
Dash, T. P.
Jena, J.
Das, S.
Maiti, C. K.
[J]. PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON VLSI DEVICE, CIRCUIT AND SYSTEM (IEEE VLSI DCS 2020), 2020, : 331 - 334
[47] 3D-carrier Profiling and Parasitic Resistance Analysis in Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors.
Eyben, P.
Ritzenthaler, R.
De Keersgieter, A.
Celano, U.
Chiarella, T.
Veloso, A.
Mertens, H.
Pena, V.
Santoro, G.
Machillot, J.
Kim, M.
Miyashita, T.
Yoshida, N.
Bender, H.
Richard, O.
Paredis, K.
Wouters, L.
Mitard, J.
Horiguchi, N.
[J]. 2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2019,
[48] SiGe Gate-All-around Nanosheet Reliability
Zhou, Huimei
Wang, Miaomiao
Bao, Ruqiang
Durfee, Curtis
Qin, Liqiao
Zhang, Jingyun
[J]. 2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2022,
[49] The next generation of gate-all-around transistors
Lishu Wu
[J]. Nature Electronics, 2023, 6 : 469 - 469
[50] Fabrication of the SiC Gate-All-Around JFET
Mochizuki, Masaya
Yamamoto, Masayuki
Umezawa, Hitoshi
Tanaka, Yasunori
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2023, 70 (09) : 4612 - 4617

← 1 2 3 4 5 →