3D-carrier Profiling and Parasitic Resistance Analysis in Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors.

被引：0

作者：

Eyben, P. ^{[1
]}

Ritzenthaler, R. ^{[1
]}

De Keersgieter, A. ^{[1
]}

Celano, U. ^{[1
]}

Chiarella, T. ^{[1
]}

Veloso, A. ^{[1
]}

Mertens, H. ^{[1
]}

Pena, V. ^{[2
]}

Santoro, G. ^{[2
]}

Machillot, J. ^{[2
]}

Kim, M. ^{[3
]}

Miyashita, T. ^{[3
]}

Yoshida, N. ^{[3
]}

Bender, H. ^{[1
]}

Richard, O. ^{[1
]}

Paredis, K. ^{[1
]}

Wouters, L. ^{[1
]}

Mitard, J. ^{[1
]}

Horiguchi, N. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[2] Appl Mat Inc, Leuven, Belgium

[3] Appl Mat Inc, 3050 Bowers Ave, Santa Clara, CA 95053 USA

来源：

2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2019年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have utilized the scalpel scanning spreading resistance microscopy (s-SSRM) technique in order to successfully extract for the first time 3D carrier distributions into multi-channel horizontal gate-all-around (GAA) silicon nanowires nMOS and pMOS transistors. Good correlation with DIBL characteristics of the device could be established, assessing the validity of the measurements. Compared to FinFET control samples, the results give a first explanation of the ON-current performance increase of GAA pMOS device. TCAD simulations confirm indeed that the nanowire confinement has a positive impact on SiGe: Si interface resistance.

引用

页数：4

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