Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization

被引：0

作者：

Ritzenthaler, R. ^{[1
]}

Mertens, H. ^{[1
]}

Pena, V. ^{[2
]}

Santoro, G. ^{[2
]}

Chasin, A. ^{[1
]}

Kenis, K. ^{[1
]}

Devriendt, K. ^{[1
]}

Mannaert, G. ^{[1
]}

Dekkers, H. ^{[1
]}

Dangol, A. ^{[1
]}

Lin, Y. ^{[3
]}

Sun, S. ^{[3
]}

Chen, Z. ^{[3
]}

Kim, M. ^{[3
]}

Machillot, J. ^{[2
]}

Mitard, J. ^{[1
]}

Yoshida, N. ^{[3
]}

Kim, N. ^{[3
]}

Mocuta, D. ^{[1
]}

Horiguchi, N. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[2] Appl Mat Inc, Leuven, Belgium

[3] Appl Mat Inc, 3050 Bowers Ave, Santa Clara, CA 95053 USA

来源：

2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report on vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs, integrated in a CMOS dual Work Function Metal Replacement Metal Gate (RMG) flow. The integration of a lower temperature STI module and a SiN liner, designed to mitigate the oxidation-induced NW size loss and improve the width/height aspect ratio and NW controllability, is validated electrically. Additionally, Si GAA devices with reduced vertical nanowire spacing are demonstrated. The challenges in terms of Work Function Metal thickness scaling are highlighted, and a thinner nMetal process with low V-TH capability and no J(G)/PBTI lifetime penalty is proposed. Electrically, these process innovations lead to a large improvement of I-ON/I-OFF performance and short channel margin. Finally, a ring oscillator circuit demonstration is shown, with a improvement of gate delay from 24ps down to 10ps at matched V-DD demonstrated.

引用

页数：4

共 50 条

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