Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

被引：0

作者：

Barraud, S. ^{[1
,2
]}

Previtali, B. ^{[1
,2
]}

Lapras, V. ^{[1
,2
]}

Vizioz, C. ^{[1
,2
]}

Hartmann, J. -M. ^{[1
,2
]}

Martinie, S. ^{[1
,2
]}

Lacord, J. ^{[1
,2
]}

Casse, M. ^{[1
,2
]}

Dourthe, L. ^{[1
,2
]}

Loup, V. ^{[1
,2
]}

Romano, G. ^{[3
]}

Rambal, N. ^{[1
,2
]}

Chalupa, Z. ^{[1
,2
]}

Bernier, N. ^{[1
,2
]}

Audoit, G. ^{[1
,2
]}

Jannaud, A. ^{[4
]}

Delaye, V. ^{[1
,2
]}

Balan, V. ^{[1
,2
]}

Rozeau, O. ^{[1
,2
]}

Ernst, T. ^{[1
,2
]}

Vinet, M. ^{[1
,2
]}

机构：

[1] CEA, LETI, Minatec Campus, F-38054 Grenoble, France

[2] Univ Grenoble Alpes, Minatec Campus, F-38054 Grenoble, France

[3] STMicroelectronics, F-38926 Crolles, France

[4] SERMA Technol, Minatec Campus, F-38054 Grenoble, France

来源：

2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, a comprehensive study going from the integration of 3D stacked nanosheets Gate-All-Around (GAA) MOSFET devices to SPICE modeling is proposed. Devices have been successfully fabricated on SOI substrates using a replacement high-kappa metal gate process and self-aligned-contacts. Back biasing is herein efficiently used to highlight a drastic improvement of electrostatics in the upper GAA Si channels. Advanced electrical characterization of these devices enabled us to calibrate a new version of physical compact model (LETI-NSP) in order to assess the performance of ring oscillators for different configurations of GAA FETs integrating up to 8 vertically stacked Si channels.

引用

页数：4

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