A reduced-area low-power low-voltage single-ended differential pair

被引：8

作者：

Mulder, J

vandeGevel, M

vanRoermund, AH

机构：

[1] Electronics Research Laboratory, Delft University of Technology, 2628 CD, Delft

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1997年 / 32卷 / 02期

关键词：

analog VLSI; CMOS analog integrated circuits; neural network hardware;

D O I：

10.1109/4.551919

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In analog very Large scale integratin ((VLSI), a high computational density is important. Area savings can be obtained by operating the MOS transistor in the triode region, thus exploiting its symmetrical nature. Applying this theory to a single ended differential pair results in an area reduction of up to a factor 1.5, which can be significant, e.g., for neural networks, where the basic cells are repeated many times on a single chip. The proposed circuit also has advantages with respect to low-power and low-voltage operation.

引用

页码：254 / 257

页数：4

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