Single-Ended Half-Swing Low-Power SRAM Design

Although memory is a critical component in general-purpose and applicatioin-specific processors, it tends to consume a large amount of power. To alleviate this power dissipation half-swing memory systems have been proposed which allow, memory to be accessed with bitlines that do not swing rail to rail. Unfortunately, half-swing memory systems have additional logic to prevent logic from being written or read at the wrong time or with the wrong level. This paper proposes a novel circuit that helps half-swing memory designs to be implemented more efficiently Moreover logic is allocated to allow the bitlines to be accessed across one side of a column as opposed to having logic that must access both sides of the memory column. Power results with TSMC SCN6M 0.18 mu m technology are explored using repeated circuit simulation and indicate up to 70% savings in total average power dissipation.