Embedded OTP fuse in CMOS logic process

被引：10

作者：

Lin, CY ^{[1
]}

Lin, CH ^{[1
]}

Ho, CH ^{[1
]}

Liao, WW ^{[1
]}

Lee, SY ^{[1
]}

Ho, MC ^{[1
]}

Wang, SC ^{[1
]}

Huang, SC ^{[1
]}

Lin, YT ^{[1
]}

Hsu, CCH ^{[1
]}

机构：

[1] Memory Technol Inc, Hsinchu 300, Taiwan

来源：

2005 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING - PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/MTDT.2005.22

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the embedded OTP fuse in standard CMOS logic compatible process without additional mask. The embedded OTP fuse can be programmed in 100us per byte and be accessed in 6ns for 32 bits at once. The 32-bit OTP fuse takes less than 0.0085mm2 in 0.25um CMOS process and has 10-year data retention at 85 degrees C.

引用

页码：13 / 15

页数：3

共 50 条

[41] A New Ultra- Low Voltage Metal Fuse for High Density OTP Applications
Wang, Li-Yu
Chen, Kuan-Ju
Yuh, Perng-Fei
Wang, Yih
Chang, Jonathan
King, Ya-Chin
Lin, Chrong Jung
2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA, 2024,
[42] CMOS process combines logic and 30V transistors
不详
ELECTRONICS WORLD, 2005, 111 (1826): : 8 - 8
[43] Advanced complementary bipolar process integrates submicron CMOS logic
Bindra, A
ELECTRONIC DESIGN, 2000, 48 (04) : 40 - 40
[44] Process Control for 45 nm CMOS logic gate patterning
Le Gratiet, Bertrand
Gouraud, Pascal
Aparicio, Enrique
Babaud, Laurene
Dabertrand, Karen
Touchet, Mathieu
Kremer, Stephanie
Chaton, Catherine
Foussadier, Franck
Sundermann, Frank
Massin, Jean
Chapon, Jean-Damien
Gatefait, Maxime
Minghetti, Blandine
de-Caunes, Jean
Boutin, Daniel
METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXII, PTS 1 AND 2, 2008, 6922 (1-2):
[45] One time programming (OTP) with zener diodes in CMOS processes
Teichmann, J
Burger, K
Hasche, W
Herrfurth, J
Täschner, G
ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, : 433 - 436
[46] High-Density Embedded 3-D Stackable Via RRAM in 16-nm FinFET CMOS Logic Process
Huang, Yao-Hung
Hsieh, Yu-Cheng
Lin, Yu-Cheng
Chih, Yue-Der
Wang, Yih
Chang, Jonathan
King, Ya-Chin
Lin, Chrong Jung
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2024, 71 (06) : 3614 - 3619
[47] Fast One-Time Programming (OTP) and a Programming Verification Solution using Zener Diodes in a Standard CMOS Process
Trontelj, Janez
INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 2014, 44 (02): : 104 - 108
[48] Design of Temporal Logic Embedded Controller for Small Oven Process
Boonpranchoo, Vichitpon
Kongratana, Viriya
Tipsuwanporn, Vittaya
Numsomran, Arjin
2011 11TH INTERNATIONAL CONFERENCE ON CONTROL, AUTOMATION AND SYSTEMS (ICCAS), 2011, : 1354 - 1357
[49] Universal High Voltage Multiplexer for CMOS OTP Memory Applications
Ng, Kwok Ping
Lee, M. C.
Chan, Wan Tim
Barsatan, Randy
Chan, Mansun
EDSSC: 2008 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, 2008, : 227 - 230
[50] Design and experimental results of a cmos flip-flop featuring embedded threshold logic
Padure, M
Cotofana, S
Vassiliadis, S
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V: BIO-MEDICAL CIRCUITS & SYSTEMS, VLSI SYSTEMS & APPLICATIONS, NEURAL NETWORKS & SYSTEMS, 2003, : 253 - 256

← 1 2 3 4 5 →