Embedded OTP fuse in CMOS logic process

被引：10

作者：

Lin, CY ^{[1
]}

Lin, CH ^{[1
]}

Ho, CH ^{[1
]}

Liao, WW ^{[1
]}

Lee, SY ^{[1
]}

Ho, MC ^{[1
]}

Wang, SC ^{[1
]}

Huang, SC ^{[1
]}

Lin, YT ^{[1
]}

Hsu, CCH ^{[1
]}

机构：

[1] Memory Technol Inc, Hsinchu 300, Taiwan

来源：

2005 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING - PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/MTDT.2005.22

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the embedded OTP fuse in standard CMOS logic compatible process without additional mask. The embedded OTP fuse can be programmed in 100us per byte and be accessed in 6ns for 32 bits at once. The 32-bit OTP fuse takes less than 0.0085mm2 in 0.25um CMOS process and has 10-year data retention at 85 degrees C.

引用

页码：13 / 15

页数：3

共 50 条

[21] Antifuse OTP Cell in a Cross-Point Array by Advanced CMOS FinFET Process
Kuo, Ren-Jay
Chang, Fu-Cheng
King, Ya-Chin
Lin, Chrong-Jung
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (04) : 1729 - 1733
[22] 3-transistor antifuse OTP ROM array using standard CMOS process
Kim, J
Lee, K
2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, : 239 - 242
[23] A 1 MUM CMOS PROCESS FOR LOGIC APPLICATIONS
OSINSKI, K
BUTLER, A
FORESTER, L
GUIDRY, D
JONKERS, A
LOOF, N
NAGALINGAM, S
DEVRIES, RP
SCHETS, G
SEAMS, C
VANDERVEEN, H
VERHULST, J
VOORS, I
PHILIPS JOURNAL OF RESEARCH, 1989, 44 (2-3) : 257 - 293
[24] A High Efficiency N Channel Single Poly OTP Cell Structure in Standard CMOS Process
Chen, Yu
Yuan, Yuan
Chen, Hualun
Zhang, Yuhua
2019 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2019,
[25] DIGITAL FUSE CIRCUIT BASED ON FLOATING GATE TECHNOLOGY IN A STANDARD CMOS PROCESS
Craciun, Mihai
Bogdan, Daniela
CAS: 2009 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2009, : 541 - +
[26] OTP on Demand - An Embedded System for User Authentication
Janakiraman, Siva
Sree, Kalavagunta Sowmya
Manasa, V. Leela
Rajagopalan, Sundararaman
Thenmozhi, K.
Amirtharajan, Rengarajan
2018 INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATION AND INFORMATICS (ICCCI), 2018,
[27] Architecture and implementation of an embedded reconfigurable logic core in CMOS 0.13/μm
Leijten-Nowak, K
Katoch, A
15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2002, : 3 - 7
[28] A Novel ReWritable One-Time-Programming OTP (RW-OTP) Realized by Dielectric-fuse RRAM Devices Featuring Ultra-High Reliable Retention and Good Endurance for Embedded Applications
Cheng, H. W.
Hsieh, E. R.
Huang, Z. H.
Chuang, C. H.
Chen, C. H.
Li, F. L.
Lo, Y. M.
Liu, C. H.
Chung, Steve S.
2018 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA), 2018,
[29] CMOS/SIMOX device and process technologies for embedded memory
NTT System Electronics Labs
NTT R&D, 10 (1079-1086):
[30] Characterization and Qualification of Deep-Submicron OTP Poly-Fuse Memory
Belova, N.
Allman, D.
Tibbitts, S.
INTERNATIONAL CONFERENCE MICRO- AND NANO-ELECTRONICS 2012, 2012, 8700

← 1 2 3 4 5 →