共 50 条
- [42] Area Efficient Diminished 2n-1 Modulo Adder using Parallel Prefix Adder JOURNAL OF ENGINEERING RESEARCH, 2022, 10 : 8 - 18
- [43] Efficient VLSI design of modulo 2n-1 adder using hybrid carry selection 2007 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, VOLS 1 AND 2, 2007, : 142 - 145
- [44] Efficient modulo 2N+1 tree multipliers for diminished-1 operands ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2003, : 200 - 203
- [45] Improved modulo-( 2n ± 3) multipliers 2013 17TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS 2013), 2013, : 31 - 35
- [47] A Simple Radix-4 Booth Encoded Modulo 2n+1 Multiplier 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 1163 - 1166
- [48] Residue adder design for the modulo set {2n-1; 2n; 2n+1-1} and its application in DCT architecture for HEVC 2022 IEEE 3RD INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS, VLSI SATA, 2022,
- [49] Improved-booth encoding for low-power multipliers ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI, 1999, : 62 - 65
- [50] Improved-booth encoding for low-power multipliers Proceedings - IEEE International Symposium on Circuits and Systems, 1999, 1