Design-Technology Interaction for Post-32 nm Node CMOS Technologies

被引：2
|
作者：
Shahidi, Ghavam G. [1 ]
机构：
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
来源：
2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2010年
关键词：
D O I：
10.1109/VLSIT.2010.5556204
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper will review the technology features in the recent and upcoming nodes and how they will impact circuit design, product performance, and migratability. It will cover the challenges and serious limitations that we will face in FEOL (increased leakage, loss of body effect), BEOL (RC, electro-migration), lithography (ever more complex design rules), and power management (end of frequency scaling, very high device count). We will talk about some possible technology solutions that will address some of the above challenges (disruptive device technologies, increased number of BEOL levels, and migration to lower voltages). Net is that scaling is expected to continue to 11 nm (at least). Design is expected to become significantly more complex.
引用
收藏
页码：143 / 144
页数：2
相关论文
共 50 条
  • [31] Variability-aware TCAD Based Design-Technology Co-Optimization Platform for 7nm Node Nanowire and Beyond
    Wang, Y.
    Cheng, B.
    Wang, X.
    Towie, E.
    Riddet, C.
    Brown, A. R.
    Amoroso, S. M.
    Wang, L.
    Reid, D.
    Liu, X.
    Kang, J.
    Asenov, A.
    2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2016,
  • [32] Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue
    Ryckaert, Julien
    PROCEEDINGS OF THE 2016 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN (ISPD'16), 2016, : 89 - 89
  • [33] On Process Variation Tolerant Low Cost Thermal Sensor Design in 32nm CMOS Technology
    Remarsu, Spandana
    Kundu, Sandip
    GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI, 2009, : 487 - 492
  • [34] Enabling Efficient Design-Technology Interaction by Spec-Driven Extraction Flow
    Chang, Huan-Lin
    Ma, Yutao
    Liu, Zhihong
    2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,
  • [35] Designing SRAM using CMOS and CNTFET at 32nm Technology
    Shrivastava, Arushi
    Damahe, Parul
    Kumbhare, Vijay Rao
    Majumder, Manoj Kumar
    2019 IEEE INTERNATIONAL SYMPOSIUM ON SMART ELECTRONIC SYSTEMS (ISES 2019), 2019, : 284 - 287
  • [36] CMOS latch metastability characterization at the 65-nm-technology node
    Bhushan, Manjul
    Ketchen, Mark B.
    Das, Koushik K.
    2008 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, CONFERENCE PROCEEDINGS, 2008, : 147 - +
  • [37] A 100 nm node CMOS technology for system-on-a-chip applications
    Imai, K
    Ono, A
    IEICE TRANSACTIONS ON ELECTRONICS, 2002, E85C (05): : 1057 - 1063
  • [38] Multilevel Interconnect Technology for 45-nm Node CMOS LSIs
    Nakata, Yoshihiro
    Ozaki, Shirou
    Kudo, Hiroshi
    FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 2010, 46 (01): : 120 - 127
  • [39] Extendibility of NiPt silicide to the 22-nm node CMOS technology
    Ohuchi, Kazuya
    Lavoie, Christian
    Murray, Conal E.
    D'Emic, Chris P.
    Lauer, Issac
    Chu, Jack O.
    Yang, Bin
    Besser, Paul
    Gignac, Lynne M.
    Bruley, Johny
    Singco, Gilbert U.
    Pagette, Francois
    Topol, Anna W.
    Rooks, Michael J.
    Bucchignano, James J.
    Narayanan, Vijay
    Khare, Mukesh
    Takayangi, Mariko
    Ishimaru, Kazunari
    Park, Dae-Gyu
    Shahidi, Ghavam
    Solomon, Paul M.
    EXTENDED ABSTRACTS 2008 INTERNATIONAL WORKSHOP ON JUNCTION TECHNOLOGY, 2008, : 150 - 153
  • [40] Multilevel interconnect technology for 45-nm node CMOS LSIs
    Nakata, Yoshihiro
    Ozaki, Shirou
    Kudo, Hiroshi
    Fujitsu Scientific and Technical Journal, 2010, 46 (01): : 120 - 127
12345