Design-Technology Interaction for Post-32 nm Node CMOS Technologies

被引：2
|
作者：
Shahidi, Ghavam G. [1 ]
机构：
[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
来源：
2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2010年
关键词：
D O I：
10.1109/VLSIT.2010.5556204
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper will review the technology features in the recent and upcoming nodes and how they will impact circuit design, product performance, and migratability. It will cover the challenges and serious limitations that we will face in FEOL (increased leakage, loss of body effect), BEOL (RC, electro-migration), lithography (ever more complex design rules), and power management (end of frequency scaling, very high device count). We will talk about some possible technology solutions that will address some of the above challenges (disruptive device technologies, increased number of BEOL levels, and migration to lower voltages). Net is that scaling is expected to continue to 11 nm (at least). Design is expected to become significantly more complex.
引用
收藏
页码：143 / 144
页数：2
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