Low Power Approximate Multiplier Using Error Tolerant Adder

被引：0
|
作者：
Cho, Jaeik [1 ]
Kim, Youngmin [1 ]
机构：
[1] Hongik Univ, Sch Elect & Elect Engn, Seoul, South Korea
来源：
2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020) | 2020年
关键词：
Enhanced Carry Predicting Error Tolerant Adder; Approximate multiplication; Carry Predicting Adder; Approximate Adder;
D O I：
10.1109/ISOCC50952.2020.9332952
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In many applications such as multimedia processing, the power may need to be lowered. Error tolerant adder is used to study carry prediction and approximate multiplication in this paper. The delay of addition between partial products and the results of speculative counters is reduced by the optimized Three-Dimensional Matrix (TDM) suggested in [1] when the speculative counters make no error. The results of the optimized TDM trees are added by the speculative adder for error tolerant computations. The power dissipation is lowered by tolerating the generated errors in the computations deliberately. By the speculative adder, the parts of LSB are approximated in total calculation. Instead of making LSB inaccurate, the total power dissipation is lowered.
引用
收藏
页码：298 / 299
页数：2
相关论文
共 50 条
  • [1] Low Power Multiplier Using Approximate Adder for Error Tolerant Applications
    Hemanth, C.
    Sangeetha, R. G.
    Kademani, Sagar
    Shahbaz Ali, Meer
    [J]. IETE JOURNAL OF RESEARCH, 2024,
  • [2] Low Power, High Speed Error Tolerant Multiplier Using Approximate Adders
    Reddy, Manikantta K.
    Kumar, Nithin Y. B.
    Sharma, Dheeraj
    Vasantha, M. H.
    [J]. 2015 19TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT), 2015,
  • [3] Approximate Conditional Carry Adder for Error Tolerant Applications
    Roy, Avishek Sinha
    Prasad, N.
    Dhar, Anindya Sundar
    [J]. 2016 20TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT), 2016,
  • [4] Power And Delay Efficient Exact Adder For Approximate Multiplier
    Kavipranesh, V. V.
    Janarthanan, J.
    Amruth, Naga T.
    Harisuriya, T. M.
    Prabhu, E.
    [J]. 2018 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI), 2018, : 1896 - 1899
  • [5] DeBAM - ERCPAA - CNN: Hardware Efficient CNN Accelerator Design Using Decoder Based Low Power Approximate Multiplier and Error Reduced Carry Prediction Approximate Adder
    Arun Kumar, K.
    Ramesh, R.
    Dhandapani, S.
    [J]. JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING, 2023, 41 (06) : 537 - 558
  • [6] Low Power Array Multiplier Using Modified Full Adder
    Srikanth, S.
    ThahiraBanu, I.
    VishnuPriya, G.
    Usha, G.
    [J]. PROCEEDINGS OF 2ND IEEE INTERNATIONAL CONFERENCE ON ENGINEERING & TECHNOLOGY ICETECH-2016, 2016, : 1041 - 1044
  • [7] Low-Power Approximate Multiplier With Error Recovery Using a New Approximate 4-2 Compressor
    Strollo, Antonio G. M.
    De Caro, Davide
    Napoli, Ettore
    Petra, Nicola
    Di Meo, Gennaro
    [J]. 2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,
  • [8] Low power, high speed approximate multiplier for error resilient applications
    Skandha Deepsita, S.
    Noor Mahammad, S.K.
    [J]. Integration, 2022, 84 : 37 - 46
  • [9] Low power, high speed approximate multiplier for error resilient applications
    Deepsita, Skandha S.
    Sk, Noor Mahammad
    [J]. INTEGRATION-THE VLSI JOURNAL, 2022, 84 : 37 - 46
  • [10] Low Power Karnaugh Map Approximate Adder for Error Compensation in Loop Accumulations
    Yang, Chunmei
    Jiao, Hailong
    [J]. 17TH IEEE INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2019), 2019,
12345