DFT techniques for memory macro with built-in ECC

被引：2

作者：

Kushida, K ^{[1
]}

Otsuka, N ^{[1
]}

Hirabayashi, O ^{[1
]}

Takeyama, Y ^{[1
]}

机构：

[1] Toshiba Co Ltd, SoC Res & Dev Ctr, Kawasaki, Kanagawa, Japan

来源：

2005 IEEE International Workshop on Memory Technology, Design, and Testing - Proceedings | 2005年

关键词：

D O I：

10.1109/MTDT.2005.19

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

DFT techniques to implement ECC circuitry on memory macro with no additional test cost are proposed. New methodology to design a hamming code matrix is used to achieve whole ECC system testing with standard memory BIST and conventional test sequence. The proposed ECC techniques are implemented in a 512Kb SRAM macro and demonstrated by hardware characterization with 90mn technology.

引用

页码：109 / 114

页数：6

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