Proposal for an all-spin logic device with built-in memory

被引:0
|
作者
Behtash Behin-Aein
Deepanjan Datta
Sayeef Salahuddin
Supriyo Datta
机构
[1] School of Electrical and Computer Engineering and NSF Network for Computational Nanotechnology (NCN) Purdue University,
[2] School of Electrical Engineering and Computer Science,undefined
[3] UC Berkeley,undefined
来源
Nature Nanotechnology | 2010年 / 5卷
关键词
D O I
暂无
中图分类号
学科分类号
摘要
The possible use of spin rather than charge as a state variable in devices for processing and storing information has been widely discussed1,2, because it could allow low-power operation and might also have applications in quantum computing. However, spin-based experiments and proposals for logic applications typically use spin only as an internal variable, the terminal quantities for each individual logic gate still being charge-based3,4,5,6,7,8. This requires repeated spin-to-charge conversion, using extra hardware that offsets any possible advantage. Here we propose a spintronic device that uses spin at every stage of its operation. Input and output information are represented by the magnetization of nanomagnets that communicate through spin-coherent channels. Based on simulations with an experimentally benchmarked model, we argue that the device is both feasible and shows the five essential characteristics9,10 for logic applications: concatenability, nonlinearity, feedback elimination, gain and a complete set of Boolean operations.
引用
收藏
页码:266 / 270
页数:4
相关论文
共 50 条
  • [1] Proposal for an all-spin logic device with built-in memory
    Behin-Aein, Behtash
    Datta, Deepanjan
    Salahuddin, Sayeef
    Datta, Supriyo
    NATURE NANOTECHNOLOGY, 2010, 5 (04) : 266 - 270
  • [2] A Proposal for a Magnetostriction-Assisted All-Spin Logic Device
    Iraei, Rouhollah Mousavi
    Dutta, Sourav
    Manipatruni, Sasikanth
    Nikonov, Dmitri E.
    Young, Ian A.
    Heron, John T.
    Naeemi, Azad
    2017 75TH ANNUAL DEVICE RESEARCH CONFERENCE (DRC), 2017,
  • [3] All-spin logic operations: Memory device and reconfigurable computing
    Patra, Moumita
    Maiti, Santanu K.
    EPL, 2018, 121 (03)
  • [4] All-Spin Logic Device With Inbuilt Nonreciprocity
    Srinivasan, Srikant
    Sarkar, Angik
    Behin-Aein, Behtash
    Datta, Supriyo
    IEEE TRANSACTIONS ON MAGNETICS, 2011, 47 (10) : 4026 - 4032
  • [5] Proposal for a graphene-based all-spin logic gate
    Su, Li
    Zhao, Weisheng
    Zhang, Yue
    Querlioz, Damien
    Zhang, Youguang
    Klein, Jacques-Olivier
    Dollfus, Philippe
    Bournel, Arnaud
    APPLIED PHYSICS LETTERS, 2015, 106 (07)
  • [6] Scaling Limits on All-Spin Logic
    Chang, Sou-Chi
    Kani, Nickvash
    Manipatruni, Sasikanth
    Nikonov, Dmitri E.
    Young, Ian A.
    Naeemi, Azad
    IEEE TRANSACTIONS ON MAGNETICS, 2016, 52 (07)
  • [7] Full-adder Circuit Design Based on All-spin Logic Device
    An, Qi
    Su, Li
    Klein, Jacques-Olivier
    Le Beux, Sebastien
    O'Connor, Ian
    Zhao, Weisheng
    PROCEEDINGS OF THE 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH 15), 2015, : 163 - 168
  • [8] Energy efficiency challenges for all-spin logic
    Hassan, Naimul
    Saha, Diptish
    Linseisen, Chandler M.
    Vyas, Vaibhav
    Joslin, Matthew
    Pai, Ashish G.
    Garcia-Sanchez, Felipe
    Friedman, Joseph S.
    MICROELECTRONICS JOURNAL, 2021, 110
  • [9] Improved Circuit Model for All-Spin Logic
    Alawein, Meshal
    Fariborzi, Hossein
    PROCEEDINGS OF THE 2016 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH), 2016, : 135 - 140
  • [10] Material Targets for Scaling All-Spin Logic
    Manipatruni, Sasikanth
    Nikonov, Dmitri E.
    Young, Ian A.
    PHYSICAL REVIEW APPLIED, 2016, 5 (01):