Architecture of Built-In Self-Test and Recovery Memory Chips

被引：0

作者：

Landrienko, V. A. ^{[1
]}

Diaa, Moamar ^{[1
]}

Ryabtsev, V. G. ^{[2
]}

Lutkina, T. Yu ^{[1
]}

机构：

[1] Cherkassy State Technol Univ, Cherkassy, Ukraine

[2] European Univ, Cherkassy Branch, Cherkassy, Ukraine

来源：

PROCEEDINGS OF IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS 2013) | 2013年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The article is devoted to increasing the coefficient of technical readiness of memory chips. The architecture of built-in self-test and repair is proposed, what allows changing a bit data of the primary array of memory cells, in which the failure is occurred, on the data coming from the outputs of an array of backup memory cells. The proposed hardware and software provide automatic reconfiguration of the data upon detection failure of chip.

引用

页数：4

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