ESD Characterization of Gate-All-Around (GAA) Si Nanowire Devices

被引：0

作者：

Chen, S. -H. ^{[1
]}

Linten, D. ^{[1
]}

Hellings, G. ^{[1
]}

Veloso, A. ^{[1
]}

Scholz, M. ^{[1
]}

Boschke, R. ^{[1
,2
]}

Groeseneken, G. ^{[1
,2
]}

Collaert, N. ^{[1
]}

Thean, A. ^{[1
]}

机构：

[1] IMEC, B-3001 Leuven, Belgium

[2] Katholieke Univ Leuven, ESAT Dept, B-3001 Leuven, Belgium

来源：

2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In CMOS scaling roadmap, gate-all-around (GAA) nanowire (NW) is a promising candidate in sub-10nm nodes. However, newly introduced process options in GAA NW technologies can result in significant impacts on intrinsic ESD performance. In this work, ESD protection devices in GAA NW architecture are studied and the corresponding 3D TCAD simulations bring an in-depth understanding.

引用

页数：4

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