A robust 65-nm node CMOS technology for wide-range Vdd operation

被引：0

作者：

Nakahara, Y ^{[1
]}

Fukai, T ^{[1
]}

Togo, M ^{[1
]}

Koyama, S ^{[1
]}

Morikuni, H ^{[1
]}

Matsuda, T ^{[1
]}

Sakamoto, K ^{[1
]}

Mineji, A ^{[1
]}

Fujiwara, S ^{[1
]}

Kunimune, Y ^{[1
]}

Nagase, M ^{[1
]}

Tamura, T ^{[1
]}

Onoda, N ^{[1
]}

Miyake, S ^{[1
]}

Yama, Y ^{[1
]}

Kudoh, T ^{[1
]}

Ikeda, M ^{[1
]}

Yamagata, Y ^{[1
]}

Yamamoto, T ^{[1
]}

Imai, K ^{[1
]}

机构：

[1] NEC Elect Corp, Adv Technol Dev Div, Sagamihara, Kanagawa 2291198, Japan

来源：

2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We have developed a highly reliable 65-nm node CMOS technology, enabling wide-range of Vdd operation including over-drive mode. Process conditions are carefully optimized from the various aspects of device reliability and performance. We have utilized oxynitride gate, arsenic-assisted phosphorus S/D ion-implantation, Ni-silicidation, stress controlled SiN layer process, and offset-spacer process in order to improve drive-current at low voltage operation and reliability at high voltage operation. Obtained drive-current are 730/310 muA/mum with off-current of 80 nA/mum at standard supply voltage of 0.9V, and 1150/550 muA/mum with off-current of 180 nA/mum at overdrive voltage of 1.2V, while satisfying strict criteria for transistor reliability.

引用

页码：281 / 284

页数：4

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