Embedded FeRAM Challenges in the 65-nm Technology Node and Beyond

被引：0

作者：

Kato, Yoshihisa ^{[1
]}

Tanaka, Hiroyuki ^{[1
]}

Isogai, Kazunori ^{[1
]}

Kaibara, Kazuhiro ^{[1
]}

Kaneko, Yukihiro ^{[1
]}

Shimada, Yasuhiro ^{[1
]}

Brubaker, Matt ^{[2
]}

Celinska, Jolanta ^{[2
]}

McMillan, Larry D. ^{[2
]}

de Araujo, Carlos. A. Paz ^{[2
]}

机构：

[1] Matsushita Elect Ind Co Ltd, Semicond Res Ctr, Osaka, Japan

[2] Symetrix Corp, Colorado Springs, CO USA

来源：

2006 15TH IEEE INTERNATIONAL SYMPOSIUM ON APPLICATIONS OF FERROELECTRICS | 2007年

关键词：

FeRAM; MOCVD; SrBi2Ta2O9; Bi4Ti3O12;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

To embedded ferroelectric random access memories in the 65-nm CMOS and beyond, three-dimensional structure and low-temperature formation have been developed.

引用

页码：78 / +

页数：2

共 50 条

[1] EPL performance in 65-nm node metallization technology and beyond
Koba, F
Tsuchida, T
Sakaue, H
Koike, K
Yamamoto, J
Iriki, N
Yamashita, H
Kageyama, S
Nasuno, T
Soda, E
Takeda, K
Kobayashi, H
Shoji, F
Okamura, H
Matsubara, Y
Arimoto, H
[J]. Emerging Lithographic Technologies IX, Pts 1 and 2, 2005, 5751 : 501 - 508
[2] Reticle CD-SEM for the 65-nm technology node and beyond
Schlueter, GWB
Nakamura, T
Matsumoto, J
Seyama, M
Whittey, JM
[J]. 24TH ANNUAL BACUS SYMPOSIUM ON PHOTOMASK TECHNOLOGY, PT 1 AND 2, 2004, 5567 : 876 - 886
[3] Mask challenges and capability development for the 65-nm device technology node: the first status report
Kim, WD
Aquino, C
Eickhoff, MD
Lim, P
Fukuhara, N
Jessen, S
Kikuchi, Y
Tanzawa, J
[J]. 23RD ANNUAL BACUS SYMPOSIUM ON PHOTOMASK TECHNOLOGY, PTS 1 AND 2, 2003, 5256 : 859 - 870
[4] BEOL processing - Copper electroplating, CMP challenges grow more complex at 65-nm node and beyond
Mathew, Varughese
Lin, Chenting
Luttmer, J. D.
Dukovic, John
[J]. MICRO, 2005, 23 (08): : 32 - +
[5] Embedded Flash on a Low-Power 65-nm Logic Technology
Fong, S.
Ariyoshi, J.
Ema, T.
[J]. IEEE ELECTRON DEVICE LETTERS, 2012, 33 (09) : 1261 - 1263
[6] Advanced CD control technology for 65-nm node dual damascene process
Nagase, Masatoshi
Maruyama, Takuya
Sekine, Makoto
[J]. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2007, 20 (03) : 245 - 251
[7] Advanced CD control technology for 65-nm node dual damascene process
Nagase, M.
Maruyama, T.
Iguchi, M.
Suzuki, M.
Tominaga, M.
Sekine, M.
[J]. ISSM 2006 CONFERENCE PROCEEDINGS- 13TH INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, 2006, : 141 - 144
[8] Challenges for inline elemental characterization at 65nm node and beyond
Godwin, M
[J]. ISSM 2005: IEEE International Symposium on Semiconductor Manufacturing, Conference Proceedings, 2005, : 487 - 490
[9] Challenges and solutions for trench lithography beyond 65nm node
Lu, Zhijian
Ho, Chi-Chien
Mason, Mark
Anderson, Andrew
Mckee, Randy
Jackson, Ricky
Zhu, Cynthia
Terry, Mark
[J]. DESIGN AND PROCESS INTEGRATION FOR MICROELECTRONIC MANUFACTURING IV, 2006, 6156
[10] Mask inspection technology for 65nm (hp) technology node and beyond
Tojo, T
Hirano, R
Inoue, H
Imai, S
Yoshioka, N
Ohira, K
Chung, DH
Terasawa, T
[J]. Characterization and Metrology for ULSI Technology 2005, 2005, 788 : 457 - 467

← 1 2 3 4 5 →