A mixed parallel neural networks computing unit implemented in FPGA

被引：0
|
作者：
Ma, XB [1 ]
Jin, LW [1 ]
Shen, DS [1 ]
Yin, JX [1 ]
机构：
[1] S China Univ Technol, Coll Elect & Informat, Guangzhou 510640, Peoples R China
来源：
PROCEEDINGS OF 2003 INTERNATIONAL CONFERENCE ON NEURAL NETWORKS & SIGNAL PROCESSING, PROCEEDINGS, VOLS 1 AND 2 | 2003年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A FPGA implementation architecture of neural network (NN) computing unit is proposed in this paper. In the computing unit, link parallelism is designed between the input layer and middle layer of NN; neuron parallelism is designed between the middle layer and output layer. Moreover, the method of hardware implementation of the sigmoid function of NN is improved and a new method for weight locating in computing unit is proposed, which can simply the implementation of the NN greatly.
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页码：324 / 327
页数：4
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