Artificial neural network engine: Parallel and parameterized architecture implemented in FPGA

被引：0
|
作者：
Carvalho, MB
Amaral, AM
Ramos, LED
Martins, CAPD
Ekel, P
机构：
[1] Pontif Catholic Univ Minas Gerais, BR-30535610 Belo Horizonte, MG, Brazil
[2] Rutgers State Univ, Piscataway, NJ 08855 USA
来源：
PATTERN RECOGNITION AND MACHINE INTELLIGENCE, PROCEEDINGS | 2005年 / 3776卷
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In this paper we present and analyze an artificial neural network hardware engine, its architecture and implementation. The engine was designed to solve performance problems of the serial software implementations. It is based on a hierarchical parallel and parameterized architecture. Taking into account verification results, we conclude that this engine improves the computational performance, producing speedups from 52.3 to 204.5 and its architectural parameterization provides more flexibility.
引用
收藏
页码：294 / 299
页数：6
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