Parallel Architecture for the Solution of Linear Equation Systems Implemented in FPGA

This paper presents a parallel architecture for the solution of linear equations based on the Division Free Gaussian Elimination Method is, presented [1]. This architecture can handle single and double data that follows the IEEE standard 754 for floating-point data. Also, it can be implemented in a FPGA Spartan 3 of Xilinx. The mathematical algorithm is, implemented in an array of processors. The main procedure inside each processor and the data distribution between processors is described. Furthermore, the synthesis of the designed modules for each processor that composed the proposed architecture is presented. The obtained algorithmic complexity is O(n(2)) using a scheme of n(2) processors that perform the solution of the linear equations set.