Artificial neural network optimization for FPGA

被引：0
|
作者：
Bonnici, Mark [1 ]
Gaff, Edward J. [1 ]
Micallef, Joseph [1 ]
Grech, Ivan [1 ]
机构：
[1] Univ Malta, Fac Engn, Dept Elect Syst Engn, Msida, Malta
来源：
2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | 2006年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes a cost effective artificial neural network implementation on an FPGA in three easy steps. Furthermore, it proposes the manner in which network layers are mapped into a particular hardware structure such that the performance and efficiency, with which the hardware resources are used, are greatly improved. A reconfigurable, parameterised neural node is presented as the basic building block for neural implementations, and is modelled in Verilog (HDL). The results show a high degree of parallelism, fast performance and most important low area resources.
引用
收藏
页码：1340 / 1343
页数：4
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