ASIC Implementation of Efficient 16-Parallel Fast FIR Algorithm Filter Structure

In this paper, a 144-tap 16-parallel Fast Finite Impulse Response (FIR) Algorithm (FFA) filter structure is designed using verilog HDL. The designed filter structure is simulated using XILINX ISE 14.7. The designed module is synthesized using CADENCE RTL Compiler and the application specific integrated circuit (ASIC) design of the proposed filter structure is implemented using CADENCE tool set on CADENCE GPDK45nm technology. By applying Fast FIR Algorithm, 65 percent of multipliers are reduced and the number of adders are increased. The adders occupy less silicon area than multipliers. Hence, the reduction in area is achieved by replacing the multipliers with adders. Further, the proposed 16 parallel FFA filter structure reduces the delay when compared to 16 parallel FIR filter structure without applying Fast FIR Algorithm. The proposed filter architecture occupies an area of 79220 sq. gm and consumes a power of 20mW at 333MHz when synthesized.