Hardware-Efficient Parallel FIR Filter Structure Based on Modified Cook-Toom Algorithm

被引:0
|
作者
Tian, Qiaoyu [1 ]
Wang, Yinan [1 ]
Liu, Guiqing [1 ]
Liu, Xiangyu [1 ]
Diao, Jietao [1 ]
Xu, Hui [1 ]
机构
[1] Natl Univ Def Technol, Coll Elect Sci, Dept Circuit & Syst, Changsha 410073, Hunan, Peoples R China
基金
中国国家自然科学基金;
关键词
Cook-Toom algorithm; fast convolution; symmetric coefficients; parallel filter; hardware-efficient;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The Cook-Toom algorithm is widely used in short-length linear convolution, which is the building block of large points convolution algorithms. This paper proposes improved parallel finite impulse response (FIR) filter structures for linear-phase FIR filter, which is based on the Cook-Toom algorithm. In the proposed structures, Cook-Toom algorithm is used to reduce the number of sub-filters, and the symmetric properties of the linear-phase FIR filter's coefficients is used to further reduce the number of multipliers in sub-filters. Compared with the reported FFA and ISCA parallel FIR filter structures, the proposed method can substantially reduce the computational complexity. Specifically, for a 8-parallel 144-tap filter, the proposed design saves 18 multipliers (5%), 45 adders (7.9%) compared with the structure based on Winograd convolution algorithm [7].
引用
收藏
页码:342 / 345
页数:4
相关论文
共 50 条
  • [1] Hardware-Efficient Parallel FIR Digital Filter Structures For Symmetric Convolutions
    Tsao, Yu-Chi
    Choi, Ken
    [J]. 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 2301 - 2304
  • [2] Hardware-Efficient Parallel Structures for Linear-Phase FIR Digital Filter
    Tian, Jingjing
    Li, Guangjun
    Li, Qiang
    [J]. 2013 IEEE 56TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2013, : 995 - 998
  • [3] Hardware-efficient pipelined programmable FIR filter design
    Chang, TS
    Jen, CW
    [J]. IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2001, 148 (06): : 227 - 232
  • [4] A Hardware-Efficient Parallel Architecture for HEVC Deblocking Filter
    Ayadi, Lella Aicha
    Boubakri, Wided
    Loukil, Hassen
    Masmoudi, Nouri
    [J]. 2019 16TH INTERNATIONAL MULTI-CONFERENCE ON SYSTEMS, SIGNALS & DEVICES (SSD), 2019, : 669 - 673
  • [5] Hardware Efficient Fast FIR Filter Based on Karatsuba Algorithm
    Kyritsis, Evangelos
    Pekmestzi, Kiamal
    [J]. 2016 5TH INTERNATIONAL CONFERENCE ON MODERN CIRCUITS AND SYSTEMS TECHNOLOGIES (MOCAST), 2016,
  • [6] Hardware-efficient implementation of digital FIR filter using fast first-order moment algorithm
    Cao, Li
    Liu, Jianguo
    Xiong, Jun
    Zhang, Jing
    [J]. MIPPR 2017: PARALLEL PROCESSING OF IMAGES AND OPTIMIZATION TECHNIQUES; AND MEDICAL IMAGING, 2018, 10610
  • [7] An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters
    Aktan, Mustafa
    Yurdakul, Arda
    Duendar, Guenhan
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2008, 55 (06) : 1536 - 1545
  • [8] Hardware-Efficient VLSI Implementation for 3-Parallel Linear-Phase FIR Digital Filter of Odd Length
    Tsao, Yu-Chi
    Choi, Ken
    [J]. 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 998 - 1001
  • [9] Hardware efficient fast parallel FIR filter structures based on iterated short convolution
    Cheng, C
    Parhi, KK
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2004, 51 (08) : 1492 - 1500
  • [10] Hardware efficient fast parallel FIR filter structures based on Iterated Short Convolution
    Cheng, C
    Parhi, KK
    [J]. 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3, PROCEEDINGS, 2004, : 361 - 364