共 50 条
- [21] Design and implementation of hardware-efficient architecture for saturation-based image dehazing algorithm [J]. Journal of Real-Time Image Processing, 2023, 20
- [23] FPGA Based Efficient Fast FIR Algorithm for Higher Order Digital FIR Filter [J]. 2012 INTERNATIONAL SYMPOSIUM ON ELECTRONIC SYSTEM DESIGN (ISED 2012), 2012, : 43 - 47
- [24] Cost-efficient multiplier-less FIR filter structure based on Modified Decor transformation [J]. 2001 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I-VI, PROCEEDINGS: VOL I: SPEECH PROCESSING 1; VOL II: SPEECH PROCESSING 2 IND TECHNOL TRACK DESIGN & IMPLEMENTATION OF SIGNAL PROCESSING SYSTEMS NEURALNETWORKS FOR SIGNAL PROCESSING; VOL III: IMAGE & MULTIDIMENSIONAL SIGNAL PROCESSING MULTIMEDIA SIGNAL PROCESSING - VOL IV: SIGNAL PROCESSING FOR COMMUNICATIONS; VOL V: SIGNAL PROCESSING EDUCATION SENSOR ARRAY & MULTICHANNEL SIGNAL PROCESSING AUDIO & ELECTROACOUSTICS; VOL VI: SIGNAL PROCESSING THEORY & METHODS STUDENT FORUM, 2001, : 1065 - 1068
- [26] Low-latency hardware-efficient memory-based design for large-order FIR digital filters [J]. 2007 6TH INTERNATIONAL CONFERENCE ON INFORMATION, COMMUNICATIONS & SIGNAL PROCESSING, VOLS 1-4, 2007, : 1254 - 1257
- [27] Hardware-efficient and accurately frequency offset compensation based on feedback structure and polar coordinates processing [J]. Optical and Quantum Electronics, 2023, 55
- [29] A hardware-efficient parallel architecture for real-time blob analysis based on run-length code [J]. Journal of Real-Time Image Processing, 2018, 15 : 657 - 672