Dual-Gate and Gate-All-Around Polycrystalline Silicon Nanowires Field Effect Transistors: Simulation and Characterization

Polycrystalline silicon nanowires (poly-SiNWs) are synthesized using sidewall spacer top-down method and classical photolithography techniques. This low-temperature (<= 600 degrees C) fabrication process is a low cost and fully compatible with planar complementary metal oxide semiconductor (CMOS) silicon technology. Independent biasing of each gate allows a possible threshold voltage control of the bottom gate transistors (BGT) and top gate transistors (TGT). Moreover, a new gate architecture passing from 2D to 3D, surrounding-gate transistors, called Gate-All-Around (GAA) where the gate circles the nanowire channel, allows a better electrostatic gate control. Numerical modeling of dual-gate structure and simulations are performed to estimate electrons and holes concentrations in the nanowire used as active layer versus applied gate voltages. Electrical performances of top and bottom-gate transistors are analyzed highlighting oxide-semiconducting nanowire interfaces difference in top and bottom gate configurations. Finally, GAA transistors characterization show that top channel conduction dominates when bias is applied on the surrounding gate.