Electrical properties of self-aligned gate-all-around polycrystalline silicon nanowires field-effect transistors

被引：12

作者：

Le Borgne, Brice ^{[1
]}

Salauen, Anne-Claire ^{[1
]}

Pichon, Laurent ^{[1
]}

机构：

[1] Univ Rennes 1, Microelect & Microsensors Dept, Rennes, France

来源：

MICROELECTRONIC ENGINEERING | 2016年 / 150卷

关键词：

Gate-all-around; MOSFET; Polycrystalline silicon; Si-nanowires; CMOS technology; THIN-FILM TRANSISTORS; PERFORMANCE; FABRICATION; MOSFET; RESISTORS; DENSITY; GROWTH; DEVICE;

D O I：

10.1016/j.mee.2015.11.001

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Low temperature (<= 600 degrees C) polycrystalline silicon nanowires field-effect transistors have been developed following a top-down approach and classical photolithography techniques. N channel transistors have been tested with a single top-gate, bottom-gate and gate-all-around architecture in order to compare their electrical performances in relation to the interface state density. Analysis shows that surrounding gate enables control of parameters such as on-current, subthreshold slope and threshold voltage and offer potential further applications. (C) 2015 Elsevier B.V. All rights reserved.

引用

页码：32 / 38

页数：7

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