Sub-15 nm gate-all-around field effect transistors on vertical silicon nanowires

被引：28
|
作者：
Larrieu, G. [1 ]
Guerfi, Y. [1 ]
Han, X. L. [2 ]
Clement, N. [2 ]
机构：
[1] Univ Toulouse, LAAS CNRS, 7 Ave Colonel Roche, F-31077 Toulouse, France
[2] IEMN UMR CNRS 8520, Ave Poincare,BP 60069, F-59652 Villeneuve Dascq, France
来源：
SOLID-STATE ELECTRONICS | 2017年 / 130卷
关键词：
3D transistors; Nanowire; Gate-all-around; MOS scaling;
D O I：
10.1016/j.sse.2016.12.008
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14 nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations in both processing (layer engineering at nanoscale), and in electrical properties (high electrostatic control, low defect level, multi-Vt platform). Furthermore, the versatility and reliability of this technology is evidenced with a CMOS inverter, providing bright perspectives for ultimate scaling. (C) 2017 Elsevier Ltd. All rights reserved.
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页码：9 / 14
页数：6
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