共 50 条
- [41] Improving soft-error tolerance of FPGA configuration bits [J]. ICCAD-2004: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2004, : 107 - 110
- [44] Soft-error tolerance analysis and optimization of nanometer circuits [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 288 - 293
- [45] Neutron soft-error simulation for semiconductor memory devices [J]. NEC RESEARCH & DEVELOPMENT, 2002, 43 (02): : 146 - 152
- [46] Soft-error simulation system and application to SRAM design [J]. FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 1996, 32 (01): : 119 - 127
- [47] Performing the soft-error rate (SER) on a TDBI chamber [J]. Advanced Reliability Modeling, 2004, : 49 - 56
- [49] Soft-Error Hardening Designs of Nanoscale CMOS Latches [J]. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2009, : 41 - 46
- [50] Generation of stressmarks for early stage soft-error modeling [J]. 2019 49TH ANNUAL IEEE/IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS - SUPPLEMENTAL VOL (DSN-S), 2019, : 42 - 48