Design of an offset-tolerant voltage sense amplifier bit-line sensing circuit for SRAM memories

被引：4
|
作者：
Licciardo, G. D. [1 ]
Cappetta, C. [1 ]
Di Benedetto, L. [1 ]
Rubino, A. [1 ]
机构：
[1] Univ Salerno, Dept Ind Engn DIIn, Via Giovanni Paolo 2,132, Salerno, Italy
来源：
ELECTRONICS LETTERS | 2016年 / 52卷 / 16期
关键词：
Timing circuits - Electric inverters - Integrated circuit design - Feedback amplifiers - Light amplifiers;
D O I：
10.1049/el.2016.1976
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The design of a new bit-line sensing scheme of SRAM memories is presented, which combines offset cancellation and compensation solutions. FCMOS inverters, brought to operate in their maximum gain region, are used to compensate the systematic offset of the sense amplifier and reduce the sensing delay. Systematic offset of the inverter amplifiers is cancelled by means of equalising feedback connections. A simulation analysis in Cadence environment and TSMC PDK demonstrates the very good potential of the proposed solution when it is compared with the recent and the established literature.
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页码：1372 / 1373
页数：2
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