A HIGH-SPEED CLAMPED BIT-LINE CURRENT-MODE SENSE AMPLIFIER

被引：68
|
作者：
BLALOCK, TN [1 ]
JAEGER, RC [1 ]
机构：
[1] AUBURN UNIV,DEPT ELECT ENGN,AUBURN,AL 36849
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 04期
关键词：
D O I：
10.1109/4.75052
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new clamped bit-line current-mode sense amplifier that maintains a low-impedance fixed potential on the bit lines is introduced. Using a general model for active-drive memory cells that include the two-transistor (2T) and three-transistor (3T) dynamic cells and the four-transistor/two-resistor (4T-2R) and six-transistor (6T) static cells, the new sense amplifier is shown to have a response speed that is insensitive to bit-line capacitance. Bit-line clamping also minimizes inter-bit-line voltage noise coupling.
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页码：542 / 548
页数：7
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