New features in Planar SiGe Channel Tunnel FETs Performance and Operation

被引：0

作者：

Le Royer, C. ^{[1
]}

Hutin, L. ^{[1
]}

Martinie, S. ^{[1
]}

Nguyen, P. ^{[1
]}

Barraud, S. ^{[1
]}

Glowacki, F. ^{[1
]}

Cristoloveanu, S. ^{[2
]}

Vinet, M. ^{[1
]}

机构：

[1] CEA, LETI, MINATEC Campus, F-38054 Grenoble, France

[2] INP Grenoble, MINATEC, MEP LAHC, Grenoble, France

来源：

2015 SILICON NANOELECTRONICS WORKSHOP (SNW) | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report the characterization of SiGe Tunnel FETs (TFETs) fabricated on SGOI with a standard CMOS process. The large gain in saturation gain (x20) is due to the threshold voltage shift and to enhanced intrinsic band-to-band tunneling injection (both related to the narrow band gap of SiGe channels). We also investigate the ambipolar signature from the ID(VDS) of TFETs which we compare to MOSFETs. A simple protocol is proposed and validated to get a rapid insight in injection mechanism at the two junctions of any FET device.

引用

页数：2

共 50 条

[41] Enhanced Performance in Epitaxial Graphene FETs With Optimized Channel Morphology
Lin, Yu-Ming
Farmer, Damon B.
Jenkins, Keith A.
Wu, Yanqing
Tedesco, Joseph L.
Myers-Ward, Rachael L.
Eddy, Charles R., Jr.
Gaskill, D. Kurt
Dimitrakopoulos, Christos
Avouris, Phaedon
IEEE ELECTRON DEVICE LETTERS, 2011, 32 (10) : 1343 - 1345
[42] A comprehensive physics based surface potential and drain current model for SiGe channel dual programmable FETs
Pandey, Priyanka
Kaur, Harsupreet
SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2022, 37 (05)
[43] Performance Evaluation of Bilayer Graphene Nanoribbon Tunnel FETs for Digital and Analog Applications
Rawat, Brajesh
Paily, Roy
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2017, 16 (03) : 411 - 416
[44] Impact of Low-Temperature Coolcube™ Process on the Performance of FDSOI Tunnel FETs
Diaz-Llorente, C.
Colinge, J. -P.
Le Royer, C.
Vinet, M.
Theodorou, C. G.
Cristoloveanu, S.
Ghibaudo, G.
2018 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2018,
[45] Performance Improvement of Poly-Si Tunnel FETs by Trap Density Reduction
Cheng-Yu, William
Chen, Yi-Hsuan
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (02) : 864 - 868
[46] Performance analysis of different SRAM cell topologies employing tunnel-FETs
Strangio, S.
Palestri, P.
Esseni, D.
Selmi, L.
Crupi, F.
2014 72ND ANNUAL DEVICE RESEARCH CONFERENCE (DRC), 2014, : 143 - +
[47] Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate
Li, Wei
Liu, Hongxia
Wang, Shulong
Chen, Shupeng
Yang, Zhaonian
NANOSCALE RESEARCH LETTERS, 2017, 12
[48] Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate
Wei Li
Hongxia Liu
Shulong Wang
Shupeng Chen
Zhaonian Yang
Nanoscale Research Letters, 2017, 12
[49] Impact of Trap-assisted Tunneling and Channel Quantization on InAs/Si Hetero Tunnel FETs
Sant, S.
Schenk, A.
Moselund, K.
Riel, H.
2016 74TH ANNUAL DEVICE RESEARCH CONFERENCE (DRC), 2016,
[50] Investigation of Cylindrical Channel Gate All Around InGaAs/InP Heterojunction Heterodielectric Tunnel FETs
Vimala, P.
Arun Samuel, T. S.
SILICON, 2021, 13 (11) : 3899 - 3907

← 1 2 3 4 5 →