New features in Planar SiGe Channel Tunnel FETs Performance and Operation

被引:0
|
作者
Le Royer, C. [1 ]
Hutin, L. [1 ]
Martinie, S. [1 ]
Nguyen, P. [1 ]
Barraud, S. [1 ]
Glowacki, F. [1 ]
Cristoloveanu, S. [2 ]
Vinet, M. [1 ]
机构
[1] CEA, LETI, MINATEC Campus, F-38054 Grenoble, France
[2] INP Grenoble, MINATEC, MEP LAHC, Grenoble, France
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We report the characterization of SiGe Tunnel FETs (TFETs) fabricated on SGOI with a standard CMOS process. The large gain in saturation gain (x20) is due to the threshold voltage shift and to enhanced intrinsic band-to-band tunneling injection (both related to the narrow band gap of SiGe channels). We also investigate the ambipolar signature from the ID(VDS) of TFETs which we compare to MOSFETs. A simple protocol is proposed and validated to get a rapid insight in injection mechanism at the two junctions of any FET device.
引用
收藏
页数:2
相关论文
共 50 条
  • [31] Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs
    Conzatti, F.
    Pala, M. G.
    Esseni, D.
    Bano, E.
    Selmi, L.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (08) : 2085 - 2092
  • [32] How Non-ideality Effects Deteriorate the Performance of Tunnel FETs
    Schenk, Andreas
    Sant, Saurabh
    Moselund, Kirsten
    Riel, Heike
    2017 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM), 2017, : 126 - 127
  • [33] Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study
    Saeidi, Ali
    Jazaeri, Farzan
    Bellando, Francesco
    Stolichnov, Igor
    Luong, Gia V.
    Zhao, Qing-Tai
    Mantl, Siegfried
    Enz, Christian C.
    Ionescu, Adrian M.
    IEEE ELECTRON DEVICE LETTERS, 2017, 38 (10) : 1485 - 1488
  • [34] Impact of Off-State Stress on SiGe-channel p-FETs in 22nm FDSOI under Large-Signal Operation
    Dang Khoa Huynh
    Quang Huy Le
    Lehmann, Steffen
    Zhao, Zhixing
    Bossu, Germain
    Arfaoui, Wafa
    Kaempfe, Thomas
    Rudolph, Matthias
    2023 18TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE, EUMIC, 2023, : 173 - 176
  • [35] Strain and Layout Management in dual Channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs
    Andrieu, F.
    Casse, M.
    Baylac, E.
    Perreau, P.
    Nier, O.
    Rideau, D.
    Berthelon, R.
    Pourchon, F.
    Pofelski, A.
    De Salvo, B.
    Gallon, C.
    Mazzocchi, V.
    Barge, D.
    Gaumer, C.
    Gourhant, O.
    Cros, A.
    Barral, V.
    Ranica, R.
    Planes, N.
    Schwarzenbach, W.
    Richard, E.
    Josse, E.
    Weber, O.
    Arnaud, F.
    Vinet, M.
    Faynot, O.
    Haond, M.
    PROCEEDINGS OF THE 2014 44TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2014), 2014, : 106 - 109
  • [36] Insights into channel potentials and electron quasi-Fermi potentials for DG tunnel FETs
    Menka
    S.Dasgupta
    Journal of Semiconductors, 2015, 36 (01) : 80 - 85
  • [37] Insights into channel potentials and electron quasi-Fermi potentials for DG tunnel FETs
    Menka
    Bulusu, Anand
    Dasgupta, S.
    JOURNAL OF SEMICONDUCTORS, 2015, 36 (01)
  • [38] SPICE Modeling of Double-Gate Tunnel-FETs Including Channel Transports
    Zhang, Lining
    Chan, Mansun
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (02) : 300 - 307
  • [39] Improved performance of SiGe nanocrystal memory with VARIOT tunnel barrier
    Liu, Yueran
    Dey, Sagnik
    Tang, Shan
    Kelly, David Q.
    Sarkar, J.
    Banerjee, Sanjay K.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (10) : 2598 - 2602
  • [40] Comparative Study of Ambipolar Characteristics for Short Channel Tunnel-FETs of Different Structures
    Paul, Dip Joti
    Abdullah-Al-Kaiser, Md.
    Khosru, Quazi D. M.
    TENCON 2017 - 2017 IEEE REGION 10 CONFERENCE, 2017, : 1680 - 1684