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- [22] Performance Analysis of Dielectric Engineered Negative Capacitance Tunnel FETs 2022 IEEE 3RD INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS, VLSI SATA, 2022,
- [25] Modeling the Effect of Surface Roughness on the Performance of Line Tunnel FETs 2017 47TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2017, : 50 - 53
- [27] Impact of the Diameter of Vertical Nanowire-Tunnel FETs with Si and SiGe Source Composition on Analog Parameters 2015 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), 2015, : 253 - 256