Performance Analysis of Dielectric Engineered Negative Capacitance Tunnel FETs

被引：0
|
作者：
Harikumar, K. R. [1 ]
Das, Midhun P. [1 ]
Shikha, U. S. [1 ]
James, Rekha K. [1 ]
Pradeep, Anju [1 ]
机构：
[1] CUSAT, Sch Engn, Kochi, Kerala, India
来源：
2022 IEEE 3RD INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS, VLSI SATA | 2022年
关键词：
Double Gate; Negative Capacitance; Dielectric Engineering; Tunnel Field Effect Transistor;
D O I：
10.1109/VLSISATA54927.2022.10046624
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
The ability to amplify the gate voltage exists in ferroelectric (FE) materials in the negative capacitance (NC) domain. A simulation-based study of NC TFETs which has Si doped HfO2 as the FE material is included in this paper. A comparative study between low-k, high-k and combination of high-k over low-k is presented here to analyze the performance metrics such as ON current, subthreshold swing (SS) and ON-OFF current ratio. The numerical simulation is performed by combining one-dimensional (1-D) Landau-Khalatnikov (LK) equation and two-dimensional (2-D) TCAD. Based on published earlier studies, this study examines the idea of NC in TFET.
引用
收藏
页数：4
相关论文
共 50 条
  • [1] Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study
    Saeidi, Ali
    Jazaeri, Farzan
    Bellando, Francesco
    Stolichnov, Igor
    Luong, Gia V.
    Zhao, Qing-Tai
    Mantl, Siegfried
    Enz, Christian C.
    Ionescu, Adrian M.
    IEEE ELECTRON DEVICE LETTERS, 2017, 38 (10) : 1485 - 1488
  • [2] Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance
    Saeidi, Ali
    Jazaeri, Farzan
    Stolichnov, Igor
    Luong, Gia V.
    Zhao, Qing-Tai
    Mantl, Siegfried
    Ionescu, Adrian M.
    NANOTECHNOLOGY, 2018, 29 (09)
  • [3] The impact of charges at the dielectric/channel interface on performance degradation in negative capacitance ferroelectric FETs
    Li, Ming-Hao
    Li, Qiang
    Hsu, Hsiao-Hsuan
    Ying, Lei-Ying
    Zhang, Bao-Ping
    Zheng, Zhi-Wei
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2023, 38 (04)
  • [4] Small signal model and analog performance analysis of negative capacitance FETs
    Eslahi, Hossein
    Hamilton, Tara J.
    Khandelwal, Sourabh
    SOLID-STATE ELECTRONICS, 2021, 186
  • [5] Implications of Dielectric Phases in Ferroelectric HfO2 Films on the Performance of Negative Capacitance FETs
    Sritharan, Mayuri
    Lee, Hyunjae
    Spinazze, Michael
    Yoon, Youngki
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2025, 24 : 67 - 72
  • [6] Mismatch of Ferroelectric Film on Negative Capacitance FETs Performance
    Liang, Yuhua
    Zhu, Zhangming
    Li, Xueqing
    Gupta, Sumeet Kumar
    Datta, Suman
    Narayanan, Vijaykrishnan
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (03) : 1297 - 1304
  • [7] Analysis of Negative Differential Resistance and RF/Analog Performance on Drain Engineered Negative Capacitance Dual Stacked-Source Tunnel FET
    Vanlalawmpuia, K.
    Medury, Aditya Sankar
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2023, 70 (03) : 1417 - 1424
  • [8] Analysis of Using Negative Capacitance FETs to Optimize Linearity Performance for Voltage Reference Generators
    Liu, Hongyi
    Zhao, Jian
    Zhang, Yuhang
    Xiao, Fan
    Liu, Yaxin
    Li, Xueqing
    Li, Xiuyan
    Li, Yongfu
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 68 (11) : 5864 - 5871
  • [9] Negative Capacitance as a Performance Booster for Tunnel FET
    Kobayashi, Masaharu
    Jang, Kyungmin
    Ueyama, Nozomu
    Hiramoto, Toshiro
    2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), 2016, : 150 - 151
  • [10] Negative Capacitance for Boosting Tunnel FET performance
    Kobayashi, Masaharu
    Jang, Kyungmin
    Ueyama, Nozomu
    Hiramoto, Toshiro
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2017, 16 (02) : 253 - 258
12345