Negative Capacitance as a Performance Booster for Tunnel FET

被引:0
|
作者
Kobayashi, Masaharu [1 ]
Jang, Kyungmin [1 ]
Ueyama, Nozomu [1 ]
Hiramoto, Toshiro [1 ]
机构
[1] Univ Tokyo, Inst Ind Sci, Tokyo 1138654, Japan
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We have investigated a super steep subthreshold slope tunnel FET by introducing negative capacitance of a ferroelectric HfO2 gate insulator, for the first time. The simulation study revealed that the electric field at the tunnel junction of the tunnel FET can be effectively enhanced by potential amplification due to the negative capacitance. The enhanced electric field increases the band-to-band tunneling rate and I-on/I-orr ratio, which results in 10x higher energy efficiency than in tunnel FET.
引用
收藏
页码:150 / 151
页数:2
相关论文
共 50 条
  • [1] Negative Capacitance for Boosting Tunnel FET performance
    Kobayashi, Masaharu
    Jang, Kyungmin
    Ueyama, Nozomu
    Hiramoto, Toshiro
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2017, 16 (02) : 253 - 258
  • [2] Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study
    Saeidi, Ali
    Jazaeri, Farzan
    Bellando, Francesco
    Stolichnov, Igor
    Luong, Gia V.
    Zhao, Qing-Tai
    Mantl, Siegfried
    Enz, Christian C.
    Ionescu, Adrian M.
    IEEE ELECTRON DEVICE LETTERS, 2017, 38 (10) : 1485 - 1488
  • [3] Transient performance estimation of charge plasma based negative capacitance junctionless tunnel FET
    Sangeeta Singh
    P.N.Kondekar
    Pawan Pal
    Journal of Semiconductors, 2016, 37 (02) : 70 - 74
  • [4] Transient performance estimation of charge plasma based negative capacitance junctionless tunnel FET
    Singh, Sangeeta
    Kondekar, P. N.
    Pal, Pawan
    JOURNAL OF SEMICONDUCTORS, 2016, 37 (02)
  • [5] Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)
    Hu, Vita Pi-Ho
    Lin, Hung-Han
    Lin, Yen-Kai
    Hu, Chenming
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (06) : 2593 - 2599
  • [6] Design and Performance Analysis of a GAA Electrostatic Doped Negative Capacitance Vertical Nanowire Tunnel FET
    Anjana Bhardwaj
    Pradeep Kumar
    Balwinder Raj
    Sunny Anand
    Journal of Electronic Materials, 2023, 52 : 3103 - 3111
  • [7] Performance Analysis of a Charge Plasma Junctionless Nanotube Tunnel FET Including the Negative Capacitance Effect
    Shruti Shreya
    Naveen Kumar
    Sunny Anand
    Intekhab Amin
    Journal of Electronic Materials, 2020, 49 : 2349 - 2357
  • [8] Performance Analysis of a Charge Plasma Junctionless Nanotube Tunnel FET Including the Negative Capacitance Effect
    Shreya, Shruti
    Kumar, Naveen
    Anand, Sunny
    Amin, Intekhab
    JOURNAL OF ELECTRONIC MATERIALS, 2020, 49 (04) : 2349 - 2357
  • [9] Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET
    Lin, Hung-Han
    Hu, Vita Pi-Ho
    PROCEEDINGS OF THE 2019 20TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2019, : 241 - 246
  • [10] Design and Performance Analysis of a GAA Electrostatic Doped Negative Capacitance Vertical Nanowire Tunnel FET
    Bhardwaj, Anjana
    Kumar, Pradeep
    Raj, Balwinder
    Anand, Sunny
    JOURNAL OF ELECTRONIC MATERIALS, 2023, 52 (05) : 3103 - 3111