On Supporting Sequential Constraints for On-Chip Generation of Post-Silicon Validation Stimuli

被引：3
|
作者：
Shi, Xiaobing [1 ]
Nicolici, Nicola [1 ]
机构：
[1] McMaster Univ, Dept Elect & Comp Engn, Hamilton, ON, Canada
来源：
2014 IEEE 23RD ASIAN TEST SYMPOSIUM (ATS) | 2014年
关键词：
D O I：
10.1109/ATS.2014.30
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Post-silicon validation plays a critical role in exposing design errors in early silicon prototypes. Its effectiveness is conditioned by in-system application of functionally-compliant stimuli for extensive periods of time. This is achieved by expanding on-the-fly randomized functional sequences, which are subjected to user-programmable constraints. In this paper we present a method to extend the existing work for on-chip generation of functionally-compliant randomized sequences with support for sequential constraints.
引用
收藏
页码：107 / 112
页数：6
相关论文
共 50 条
  • [21] Constrained Signal Selection for Post-Silicon Validation
    Basu, Kanad
    Mishra, Prabhat
    Patra, Priyadarsan
    2012 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT), 2012, : 71 - 75
  • [22] Signal Selection Heuristics for Post-Silicon Validation
    Tummala, Suprajaa
    Liu, Xiaobang
    Vemuri, Ranga
    PROCEEDINGS OF THE TWENTYFIRST INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2020), 2020, : 401 - 407
  • [23] Efficient Hierarchical Post-Silicon Validation and Debug
    Kalimuthu, Pandy
    Basu, Kanad
    Schafer, Benjamin Carrion
    2021 34TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2021 20TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID & ES 2021), 2021, : 258 - 263
  • [24] On Multiplexed Signal Tracing for Post-Silicon Validation
    Liu, Xiao
    Xu, Qiang
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2013, 32 (05) : 748 - 759
  • [25] Reaching Coverage Closure in Post-silicon Validation
    Adir, Allon
    Nahir, Amir
    Ziv, Avi
    Meissner, Charles
    Schumann, John
    HARDWARE AND SOFTWARE: VERIFICATION AND TESTING, 2011, 6504 : 60 - +
  • [26] Post-Silicon Validation of Multiprocessor Memory Consistency
    Mammo, Biruk W.
    Bertacco, Valeria
    DeOrio, Andrew
    Wagner, Ilya
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (06) : 1027 - 1037
  • [27] Interactive Analysis of Post-Silicon Validation Data
    Lalama, Andres
    Knittel, Johannes
    Koch, Steffen
    Weiskopf, Daniel
    Ertl, Thomas
    Rottacker, Sarah
    Latty, Raphael
    Rivoir, Jochen
    2022 FIRST INTERNATIONAL WORKSHOP ON VISUALIZATION IN TESTING OF HARDWARE, SOFTWARE, AND MANUFACTURING (TESTVIS 2022), 2022, : 8 - 14
  • [28] Bridging Pre-Silicon Verification and Post-Silicon Validation
    Nahir, Amir
    Ziv, Avi
    Galivanche, Rajesh
    Hu, Alan
    Abramovici, Miron
    Bentley, Bob
    Bertacco, Valeria
    Camilleri, Albert
    Foster, Harry
    Kapoor, Shakti
    PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 94 - 95
  • [29] On-Chip Detection of Process Shift and Process Spread for Post-Silicon Diagnosis and Model-Hardware Correlation
    Islam, A. K. M. Mahfuzul
    Onodera, Hidetoshi
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2013, E96D (09) : 1971 - 1979
  • [30] Hierarchical Trigger Generation for Post-silicon Debugging
    Neishaburi, M. H.
    Zilic, Zeljko
    2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2011, : 378 - 381
12345