On Supporting Sequential Constraints for On-Chip Generation of Post-Silicon Validation Stimuli

被引:3
|
作者
Shi, Xiaobing [1 ]
Nicolici, Nicola [1 ]
机构
[1] McMaster Univ, Dept Elect & Comp Engn, Hamilton, ON, Canada
关键词
D O I
10.1109/ATS.2014.30
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Post-silicon validation plays a critical role in exposing design errors in early silicon prototypes. Its effectiveness is conditioned by in-system application of functionally-compliant stimuli for extensive periods of time. This is achieved by expanding on-the-fly randomized functional sequences, which are subjected to user-programmable constraints. In this paper we present a method to extend the existing work for on-chip generation of functionally-compliant randomized sequences with support for sequential constraints.
引用
收藏
页码:107 / 112
页数:6
相关论文
共 50 条
  • [31] A Survey on Post-Silicon Functional Validation for Multicore Architectures
    Jayaraman, Padma
    Parthasarathi, Ranjani
    ACM COMPUTING SURVEYS, 2017, 50 (04)
  • [32] QED Post-Silicon Validation and Debug Invited Abstract
    Lin, David
    Mitra, Subhasish
    2014 14TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC), 2014, : 62 - 62
  • [33] ISTA: An Embedded Architecture for Post-silicon Validation in Processors
    Lei, Ting
    He, Hu
    Sun, Yihe
    2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 593 - 596
  • [34] Dynamic Trace Signal Selection for Post-Silicon Validation
    Han, Kihyuk
    Yang, Joon-Sung
    Abraham, Jacob A.
    2013 26TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2013 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2013, : 302 - 307
  • [35] On bypassing blocking bugs during post-silicon validation
    Daoud, Ehab Anis
    Nicolici, Nicola
    PROCEEDINGS OF THE 13TH IEEE EUROPEAN TEST SYMPOSIUM: ETS 2008, 2008, : 69 - 74
  • [36] Post-Silicon Validation and Calibration of Hardware Security Primitives
    Xu, Xiaolin
    Suresh, Vikram
    Kumar, Raghavan
    Burleson, Wayne
    2014 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2014, : 29 - 34
  • [37] Post-Silicon Validation in the SoC Era: A Tutorial Introduction
    Mishra, Prabhat
    Ray, Sandip
    Morad, Ronny
    Ziv, Avi
    IEEE DESIGN & TEST, 2017, 34 (03) : 68 - 92
  • [38] Space Sensitive Cache Dumping for Post-silicon Validation
    Chandran, Sandeep
    Sarangi, Smruti R.
    Panda, Preeti Ranjan
    DESIGN, AUTOMATION & TEST IN EUROPE, 2013, : 497 - 502
  • [39] WiND: An Efficient Post-Silicon Debug Strategy for Network on Chip
    Rout, Sidhartha Sankar
    Deb, Sujay
    Basu, Kanad
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2021, 40 (11) : 2372 - 2385
  • [40] Functional Post-Silicon Diagnosis and Debug for Networks-on-Chip
    Abdel-Khalek, Rawan
    Bertacco, Valeria
    2012 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2012, : 557 - 563