A zeroing cell-to-cell interference page architecture with temporary LSB storing program scheme for sub-40nm MLC NAND flash memories and beyond

被引：17

作者：

Park, Ki-Tae ^{[1
]}

Kang, Myounggon ^{[1
]}

Kim, Doogon ^{[1
]}

Hwang, Soonwook ^{[1
]}

Lee, Yeong-Taek ^{[1
]}

Kim, Changhyun ^{[1
]}

Kim, Kinam ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Memory Business, ATD, Semicond R&D Ctr, Hwasung City 445701, Gyeunggi Do, South Korea

来源：

2007 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIC.2007.4342709

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new page architecture with temporary LSB storing program scheme is presented as a breakthrough solution for sub-40nm FG (Floating-gate) MLC NAND flash memories and beyond. Without program speed degradation, the proposed method is able to eliminate 100% BL cell-to-cell and almost 50% WL cell-to-cell coupling interferences which are well known as a most critical scaling barrier for FG NAND flash memories.

引用

页码：188 / 189

页数：2

共 6 条

[1] A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories
Park, Ki-Tae
Kang, Myounggon
Kim, Doogon
Hwang, Soon-Wook
Choi, Byung Yong
Lee, Yeong-Taek
Kim, Changhyun
Kim, Kinam
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (04) : 919 - 928
[2] Degradation Mechanisms of the Program Characteristics of 10 nm NAND Flash Memories Due to Cell-to-Cell Interference
Ryu, Ju Tae
Kim, Tae Whan
[J]. JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2013, 13 (09) : 6420 - 6423
[3] Minimizing Cell-to-Cell interference by Exploiting Differential Bit Impact Characteristics of Scaled MLC NAND Flash Memories
Di, Yejia
Shi, Liang
Gao, Congming
Wu, Kaijie
Xue, Chun Jason
Sha, Edwin H. M.
[J]. 2016 5TH NON-VOLATILE MEMORY SYSTEMS AND APPLICATIONS SYMPOSIUM (NVMSA), 2016,
[4] ADVANCED HOT-CARRIER INJECTION PROGRAMMING SCHEME FOR SUB 20NM NAND FLASH CELL AND BEYOND
Ahn, Sang-Tae
Mun, Kyungsik
Lee, Keun Woo
Cho, Gyuseog
Park, Sung-Kye
Lee, Seokkiu
Hong, Sungjoo
[J]. 2012 4TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW), 2012,
[5] Array Architecture of Floating Body Cell (FBC) with Quasi-Shielded Open Bit Line Scheme for sub-40nm Node
Fujita, Katsuyuki
Ohsawa, Takashi
Fukuda, Ryo
Matsuoka, Fumiyoshi
Higashi, Tomoki
Shino, Tomoaki
Watanabe, Yohji
[J]. 2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2008, : 31 - +
[6] Scalable wordline shielding scheme using dummy cell beyond 40 nm NAND flash memory for eliminating abnormal disturb of edge memory cell
Park, Ki-Tae
Lee, SeungChul
Sel, Jong-Sun
Choi, Jungdal
Kim, Kinam
[J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (4B): : 2188 - 2192

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