Array Architecture of Floating Body Cell (FBC) with Quasi-Shielded Open Bit Line Scheme for sub-40nm Node

被引：0

作者：

Fujita, Katsuyuki ^{[1
]}

Ohsawa, Takashi ^{[1
]}

Fukuda, Ryo ^{[1
]}

Matsuoka, Fumiyoshi ^{[1
]}

Higashi, Tomoki ^{[2
]}

Shino, Tomoaki ^{[1
]}

Watanabe, Yohji ^{[1
]}

机构：

[1] Toshiba Co Ltd, Semicond Co, Ctr Semicond Res & Dev, Yokohama, Kanagawa, Japan

[2] Toshiba Microelect Corp, Div Memory, Yokohama, Kanagawa, Japan

来源：

2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Cell array architecture for floating body RAM of 35nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit fine coupling noise in open bit line architecture without degrading the cycle time of the RAM.

引用

页码：31 / +

页数：2