Scalable wordline shielding scheme using dummy cell beyond 40 nm NAND flash memory for eliminating abnormal disturb of edge memory cell

A scalable wordline shielding scheme using dummy cell in NAND flash memory is presented to eliminate abnormal disturb of edge memory cell which causes to degradation of NAND flash performance. The proposed NAND flash is also able to improve more NAND scaling compared to conventional NAND string beyond sub-40 nm technology node. By using a proposed program scheme which includes an optimized bias voltage and adjusted V-th of dummy cell, almost abnormal disturbance of edge memory cell is removed and over 58% capacitive coupling noise between select transistor and edge memory cell can be reduced from both simulation and experimental results which used 63 nm NAND flash technology. The proposed NAND flash also improves V-th distribution of memory cell by providing almost equal operation conditions for all memory cells in NAND string.