Improving read disturb characteristics by using double common source line and dummy switch architecture in multi level cell NAND flash memory with low power consumption

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Inter-University Semiconductor Research Center, School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea, Republic of ^{[1
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不详 ^{[2
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不详 ^{[3
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Jpn. J. Appl. Phys. | / 4 PART 2卷

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Engineering Village;

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摘要：

Conventional schemes - Low-power consumption - Multi level cell (MLC) - Multilevel cell - NAND flash memory - NAND structures - Switch architectures - Technology nodes

引用

共 3 条

[1] Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption
Kang, Myounggon
Park, Ki-Tae
Song, Youngsun
Lim, Youngho
Suh, Kang-Deog
Shin, Hyungcheol
[J]. JAPANESE JOURNAL OF APPLIED PHYSICS, 2011, 50 (04)
[2] Improving the cell characteristics using low-k gate Spacer in 1Gb NAND flash memory
Kang, Daewoong
Jang, Sungnam
Lee, Kyongjoo
Kim, Jinjoo
Kwon, Hyukje
Lee, Wonseong
Park, Byung-Gook
Lee, Jong Duk
Shin, Hyungcheol
[J]. 2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2006, : 744 - +
[3] Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell VTH Optimization of Ferroelectric (Fe)-NAND Flash Memories for Highly Reliable and Low Power Enterprise Solid-State Drives (SSDs)
Hatanaka, Teruyoshi
Takahashi, Mitsue
Sakai, Shigeki
Takeuchi, Ken
[J]. IEICE TRANSACTIONS ON ELECTRONICS, 2011, E94C (04): : 539 - 547

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