Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell VTH Optimization of Ferroelectric (Fe)-NAND Flash Memories for Highly Reliable and Low Power Enterprise Solid-State Drives (SSDs)

被引:4
|
作者
Hatanaka, Teruyoshi [1 ]
Takahashi, Mitsue [2 ]
Sakai, Shigeki [2 ]
Takeuchi, Ken [1 ]
机构
[1] Univ Tokyo, Tokyo 1138656, Japan
[2] Natl Inst Adv Ind Sci & Technol, Tsukuba, Ibaraki 3058568, Japan
来源
IEICE TRANSACTIONS ON ELECTRONICS | 2011年 / E94C卷 / 04期
关键词
NAND flash memory; ferroelectric; solid-state drive; SSD;
D O I
10.1587/transele.E94.C.539
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents an improvement of the memory cell reliability by the memory cell V-TH optimization of the ferroelectric (Fe)-NAND flash memory. The effects of the memory cell V-TH on the reliability of the Fe-NAND flash memory are experimentally analyzed for the first time. The reliability is evaluated by the measured V-TH shift due to the read disturb, program disturb and data retention. Three types of Fe-NAND flash memory cells, a positive, zero and negative V-TH memory cell, are defined on the basis of the memory cell V-TH. The middle of V-TH of programmed and erased states is I V, 0 V and -0.3 V in a positive, zero and negative V-TH memory cell, respectively. The V-TH shift of the positive, zero and negative V-TH memory cells show similar characteristics in the program/erase and the V-PASS and V-PGM disturbs because the external electric field is so high that the internal depolarization field does not affect the V-TH shift. On the other hand, in the data retention, the V-TH shift of the three types of V-TH memory cells show different characteristics. The reliability of the Fe-NAND flash memory is best optimized in the zeroV(TH) memory cell. In the proposed zero V-TH Fe-NAND flash memory cell scheme, the measured V-TH shift due to the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively, compared with conventional positive V-TH Fe-NAND flash memory cell scheme. Contrarily, in the negative VTH memory cell, the V-TH shift during the data retention is 0.49 V and unacceptably large because of the depolarization field. The conventional positive V-TH memory cell suffers from a sever read and program disturb. The measured results are drastically different from those of the conventional floating-gate NAND flash memory cell where the negative V-TH memory cell is most suitable in terms of the reliability.
引用
收藏
页码:539 / 547
页数:9
相关论文
共 5 条
  • [1] Uniform and Concentrated Read Disturb Effects in Mid-1X TLC NAND Flash Memories for Enterprise Solid State Drives
    Zambelli, Cristian
    Olivo, Piero
    Crippa, Luca
    Marelli, Alessia
    Micheloni, Rino
    [J]. 2017 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2017,
  • [2] Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs)
    Takeuchi, Ken
    Hatanaka, Teruyoshi
    Tanakamaru, Shuhei
    [J]. IEICE ELECTRONICS EXPRESS, 2012, 9 (08): : 779 - 794
  • [3] System-Level Error Correction by Read-Disturb Error Model of 1Xnm TLC NAND Flash Memory for Read-Intensive Enterprise Solid-State Drives (SSDs)
    Deguchi, Yoshiaki
    Tokutomi, Tsukasa
    Takeuchi, Ken
    [J]. 2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2016,
  • [4] Ferroelectric(Fe)-NAND Flash Memory with Non-volatile Page Buffer for Data Center Application Enterprise Solid-State Drives (SSD)
    Hatanaka, Teruyoshi
    Yajima, Ryoji
    Horiuchi, Takeshi
    Wang, Shouyu
    Zhang, Xizhen
    Takahashi, Mitsue
    Sakai, Shigeki
    Takeuchi, Ken
    [J]. 2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2009, : 78 - 79
  • [5] Ferroelectric (Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives
    Hatanaka, Teruyoshi
    Yajima, Ryoji
    Horiuchi, Takeshi
    Wang, Shouyu
    Zhang, Xizhen
    Takahashi, Mitsue
    Sakai, Shigeki
    Takeuchi, Ken
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (10) : 2156 - 2164